PIC16LC773-04SLASHSP datasheet(114/200 Pages) MICROCHIP

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PIC16C77X

DS30275A-page 114

Advance Information

FIGURE 10-2: REFCON: VOLTAGE REFERENCE CONTROL REGISTER

10.1

Bandgap Voltage Reference

The bandgap module generates a stable voltage refer-

ence of 1.22V over a range of temperatures and device

supply voltages. This module is enabled anytime any of

the following are enabled:

• Brown-out Reset

• Low-voltage Detect

• Either of the internal analog references (VRH,

VRL)

Whenever the above are all disabled, the bandgap

module is disabled and draws no current.

10.2

Internal VREF for A/D Converter

The bandgap output voltage is used to generate two

stable references for the A/D converter module. These

references are enabled in software to provide the user

with the means to turn them on and off in order to min-

imize current consumption. Each reference can be indi-

vidually enabled.

The 4.096V reference (VRH) is enabled with control bit

VRHEN (REFCON<7>). When this bit is set, the gain

amplifier is enabled. After a specified start-up time a

stable reference of 4.096V is generated and can be

used by the A/D converter as the VRH input.

The 2.048V reference (VRL) is enabled by setting con-

trol bit VRLEN (REFCON<6>). When this bit is set, the

gain amplifier is enabled. After a specified start up time

a stable reference of 2.048V is generated and can be

used by the A/D converter as the VRL input.

Each voltage reference can source/sink up to 5 mA of

current.

Each reference, if enabled, can be presented on an

external pin by setting the VRHOEN (high reference

output enable) or VRLOEN (low reference output

enable) control bit. If the reference is not enabled, the

VRHOEN and VRLOEN bits will have no effect on the

corresponding pin. The device specific pin can then be

used as general purpose I/O.

R/W-0

U-0

VRHEN

VRLEN

VRHOEN

VRLOEN

—

R = Readable bit

W = Writable bit

U = Unimplemented

bit, read as ‘0’

- n =Value at POR

reset

bit7

bit0

bit 7:

VRHEN: Voltage Reference High Enable bit (VRH = 4.096V)

1 = Enabled, powers up reference generator

0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL

bit 6:

VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V)

1 = Enabled, powers up reference generator

0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH

bit 5:

VRHOEN: High Voltage Reference Output Enable bit

1 = Enabled, VRH analog reference is presented on RA3 if enabled (VRHEN = 1)

0 = Disabled, analog reference is used internally only

bit 4:

VRLOEN: Low Voltage Reference Output Enable bit

1 = Enabled, VRL analog reference is presented on RA2 if enabled (VRLEN = 1)

0 = Disabled, analog reference is used internally only

bit 3-0: Unimplemented: Read as '0’

Note:

If VRH or VRL is enabled and the other ref-

erence (VRL or VRH), the BOR, and the

LVD modules are not enabled, the band-

gap will require a start-up time of no more

than 50

µs before the bandgap reference is

stable. Before using the internal VRH or

VRL reference, ensure that the bandgap

reference voltage is stable by monitoring

the BGST bit in the LVDCON register. The

voltage references will not be reliable until

the bandgap is stable as shown by BGST

being set.

PIC16LC773-04/SP Datasheet(PDF) 114 Page - Microchip Technology

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