PIC16LC773-04SLASHSP datasheet(166/200 Pages) MICROCHIP

166 / 200 page

PIC16C77X

DS30275A-page 166

Advance Information

FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE)

TABLE 15-10

A/D CONVERSION REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130*

TAD

A/D clock period

1.6

——

µs

Tosc based, VREF

≥ 2.5V

3.0

—

µs

Tosc based, VREF full range

130*

TAD

A/D Internal RC

oscillator period

3.0

6.0

9.0

µs

ADCS1:ADCS0 = 11 (RC mode)

At VDD = 2.5V

2.0

4.0

6.0

µsAt VDD = 5.0V

131*

TCNV

Conversion time (not

including

acquisition time)

(Note 1)

—

13TAD

—TAD

Set GO bit to new data in A/D result

132*

TACQ

Acquisition Time

Note 2

11.5

—

µs

The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1LSb (i.e

1mV @ 4.096V) from the last sam-

pled voltage (as stated on CHOLD).

134*

TGO

Q4 to A/D clock start

—

TOSC/2

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 11.6 for minimum conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1/2 Tcy

134

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