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PIC16LC773-04/SP Datasheet(PDF) 190 Page - Microchip Technology |
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PIC16LC773-04/SP Datasheet(HTML) 190 Page - Microchip Technology |
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190 / 200 page  PIC16C77X DS30275A-page 190 Preliminary © 1999 Microchip Technology Inc. E Errata ................................................................................... 4 External Power-on Reset Circuit ...................................... 132 F Firmware Instructions ....................................................... 143 Flowcharts Acknowledge .............................................................. 86 Master Receiver ......................................................... 83 Master Transmit ......................................................... 80 Restart Condition ....................................................... 77 Start Condition ........................................................... 75 Stop Condition ........................................................... 88 FSR Register .......................................................... 13, 14, 15 Fuzzy Logic Dev. System ( fuzzyTECH ®-MP) .................. 147 G GCE ................................................................................... 56 General Call Address Sequence ........................................ 69 General Call Address Support ........................................... 69 General Call Enable bit, GCE ............................................ 56 I I/O Ports ............................................................................. 27 I2C ...................................................................................... 63 I2C Master Mode Receiver Flowchart ................................ 83 I2C Master Mode Reception ............................................... 82 I2C Master Mode Restart Condition ................................... 76 I2C Mode Selection ............................................................ 63 I2C Module Acknowledge Flowchart ............................................. 86 Acknowledge Sequence timing .................................. 85 Addressing ................................................................. 64 Baud Rate Generator ................................................. 73 Block Diagram ............................................................ 71 BRG Block Diagram ................................................... 73 BRG Reset due to SDA Collision ............................... 92 BRG Timing ............................................................... 73 Bus Arbitration ........................................................... 90 Bus Collision .............................................................. 90 Acknowledge ...................................................... 90 Restart Condition ............................................... 93 Restart Condition Timing (Case1) ...................... 93 Restart Condition Timing (Case2) ...................... 93 Start Condition ................................................... 91 Start Condition Timing ................................. 91, 92 Stop Condition ................................................... 94 Stop Condition Timing (Case1) .......................... 94 Stop Condition Timing (Case2) .......................... 94 Transmit Timing ................................................. 90 Bus Collision timing .................................................... 90 Clock Arbitration ......................................................... 89 Clock Arbitration Timing (Master Transmit) ................ 89 Conditions to not give ACK Pulse .............................. 64 General Call Address Support ................................... 69 Master Mode .............................................................. 71 Master Mode 7-bit Reception timing .......................... 84 Master Mode Operation ............................................. 72 Master Mode Start Condition ..................................... 74 Master Mode Transmission ........................................ 79 Master Mode Transmit Sequence .............................. 72 Master Transmit Flowchart ........................................ 80 Multi-Master Communication ..................................... 90 Multi-master Mode ..................................................... 72 Operation ................................................................... 63 Repeat Start Condition timing .................................... 76 Restart Condition Flowchart ...................................... 77 Slave Mode ................................................................ 64 Slave Reception ........................................................ 65 Slave Transmission ................................................... 65 SSPBUF .................................................................... 64 Start Condition Flowchart .......................................... 75 Stop Condition Flowchart ........................................... 88 Stop Condition Receive or Transmit timing ............... 87 Stop Condition timing ................................................. 87 Waveforms for 7-bit Reception .................................. 65 Waveforms for 7-bit Transmission ............................. 66 I2C Module Address Register, SSPADD ........................... 64 I2C Slave Mode .................................................................. 64 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ......... 145 ID Locations ............................................................. 127, 141 In-Circuit Serial Programming (ICSP) ...................... 127, 141 INDF .................................................................................. 15 INDF Register .............................................................. 13, 14 Indirect Addressing ............................................................ 25 FSR Register ............................................................. 11 Instruction Format ............................................................ 143 Instruction Set .................................................................. 143 Summary Table ....................................................... 144 INTCON ............................................................................. 15 INTCON Register ............................................................... 18 GIE Bit ....................................................................... 18 INTE Bit ..................................................................... 18 INTF Bit ..................................................................... 18 PEIE Bit ..................................................................... 18 RBIE Bit ..................................................................... 18 RBIF Bit ............................................................... 18, 30 T0IE Bit ...................................................................... 18 T0IF Bit ...................................................................... 18 Inter-Integrated Circuit (I2C) .............................................. 53 internal sampling switch (Rss) impedence ...................... 123 Interrupt Sources ..................................................... 127, 137 Block Diagram ......................................................... 137 Capture Complete (CCP) ........................................... 48 Compare Complete (CCP) ......................................... 49 Interrupt on Change (RB7:RB4 ) ............................... 30 RB0/INT Pin, External ...................................... 7, 8, 138 TMR0 Overflow .................................................. 40, 138 TMR1 Overflow .................................................... 41, 43 TMR2 to PR2 Match .................................................. 46 TMR2 to PR2 Match (PWM) ................................ 45, 50 USART Receive/Transmit Complete ......................... 97 Interrupts, Context Saving During .................................... 138 Interrupts, Enable Bits A/D Converter Enable (ADIE Bit) ............................... 19 CCP1 Enable (CCP1IE Bit) ................................. 19, 48 CCP2 Enable (CCP2IE Bit) ....................................... 21 Global Interrupt Enable (GIE Bit) ....................... 18, 137 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) ........................................................... 18, 138 Peripheral Interrupt Enable (PEIE Bit) ....................... 18 PSP Read/Write Enable (PSPIE Bit) ......................... 19 RB0/INT Enable (INTE Bit) ........................................ 18 SSP Enable (SSPIE Bit) ............................................ 19 TMR0 Overflow Enable (T0IE Bit) ............................. 18 TMR1 Overflow Enable (TMR1IE Bit) ........................ 19 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 USART Receive Enable (RCIE Bit) ........................... 19 USART Transmit Enable (TXIE Bit) ........................... 19 |
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