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PIC16LC773-04/SP Datasheet(PDF) 194 Page - Microchip Technology |
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PIC16LC773-04/SP Datasheet(HTML) 194 Page - Microchip Technology |
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194 / 200 page  PIC16C77X DS30275A-page 194 Preliminary © 1999 Microchip Technology Inc. Overflow Interrupt ................................................ 41, 43 RC0/T1OSO/T1CKI Pin ........................................... 7, 9 RC1/T1OSI/CCP2 Pin .............................................. 7, 9 Special Event Trigger (CCP) ................................ 43, 49 T1CON Register ........................................................ 41 TMR1H Register ........................................................ 41 TMR1L Register ......................................................... 41 Timer2 Block Diagram ............................................................ 46 PR2 Register ........................................................ 45, 50 SSP Clock Shift .................................................... 45, 46 T2CON Register ........................................................ 45 TMR2 Register ........................................................... 45 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20 TMR2 to PR2 Match Interrupt ........................ 45, 46, 50 Timing Diagrams Acknowledge Sequence Timing ................................. 85 Baud Rate Generator with Clock Arbitration .............. 73 BRG Reset Due to SDA Collision .............................. 92 Brown-out Reset ...................................................... 163 Bus Collision Start Condition Timing ....................................... 91 Bus Collision During a Restart Condition (Case 1) .... 93 Bus Collision During a Restart Condition (Case2) ..... 93 Bus Collision During a Start Condition (SCL = 0) ...... 92 Bus Collision During a Stop Condition ....................... 94 Bus Collision for Transmit and Acknowledge ............. 90 Capture/Compare/PWM ........................................... 169 CLKOUT and I/O ...................................................... 162 External Clock Timing .............................................. 161 I2C Master Mode First Start bit timing ........................ 74 I2C Master Mode Reception timing ............................ 84 I2C Master Mode Transmission timing ....................... 81 Master Mode Transmit Clock Arbitration .................... 89 Power-up Timer ....................................................... 163 Repeat Start Condition ............................................... 76 Reset ........................................................................ 163 Slave Synchronization ............................................... 60 Start-up Timer .......................................................... 163 Stop Condition Receive or Transmit .......................... 87 Time-out Sequence on Power-up .................... 135, 136 Timer0 ...................................................................... 168 Timer1 ...................................................................... 168 USART Asynchronous Master Transmission ........... 103 USART Synchronous Receive ................................. 171 USART Synchronous Reception .............................. 109 USART Synchronous Transmission ................ 108, 171 USART, Asynchronous Reception ........................... 105 Wake-up from SLEEP via Interrupt .......................... 141 Watchdog Timer ....................................................... 163 TMR0 ................................................................................. 15 TMR0 Register ................................................................... 13 TMR1H ............................................................................... 15 TMR1H Register ................................................................ 13 TMR1L ............................................................................... 15 TMR1L Register ................................................................. 13 TMR2 ................................................................................. 15 TMR2 Register ................................................................... 13 TRISA Register .......................................................... 14, 126 TRISB Register .......................................................... 14, 126 TRISC Register .................................................................. 14 TRISD Register .................................................................. 14 TRISE Register .................................................... 14, 35, 126 IBF Bit ........................................................................ 35 IBOV Bit ..................................................................... 35 OBF Bit ...................................................................... 35 PSPMODE Bit ................................................ 34, 35, 37 TXREG .............................................................................. 15 TXSTA Register ................................................................. 97 BRGH Bit ............................................................. 97, 99 CSRC Bit ................................................................... 97 SYNC Bit ................................................................... 97 TRMT Bit .................................................................... 97 TX9 Bit ....................................................................... 97 TX9D Bit .................................................................... 97 TXEN Bit .................................................................... 97 U UA ...................................................................................... 54 Universal Synchronous Asynchronous Receiver Transmitter (USART) Asynchronous Receiver Setting Up Reception ....................................... 104 Timing Diagram ............................................... 105 Update Address, UA .......................................................... 54 USART ............................................................................... 97 Asynchronous Mode ................................................ 102 Master Transmission ....................................... 103 Receive Block Diagram ................................... 105 Transmit Block Diagram .................................. 102 Baud Rate Generator (BRG) ..................................... 99 Baud Rate Error, Calculating ............................. 99 Baud Rate Formula ........................................... 99 Baud Rates, Asynchronous Mode (BRGH=0) . 100 Baud Rates, Asynchronous Mode (BRGH=1) . 101 Baud Rates, Synchronous Mode ..................... 100 High Baud Rate Select (BRGH Bit) ............. 97, 99 Sampling ............................................................ 99 Clock Source Select (CSRC Bit) ................................ 97 Continuous Receive Enable (CREN Bit) .................... 98 Framing Error (FERR Bit) .......................................... 98 Mode Select (SYNC Bit) ............................................ 97 Overrun Error (OERR Bit) .......................................... 98 RC6/TX/CK Pin ........................................................ 7, 9 RC7/RX/DT Pin ........................................................ 7, 9 RCSTA Register ........................................................ 98 Receive Data, 9th bit (RX9D Bit) ............................... 98 Receive Enable (RCIE Bit) ........................................ 19 Receive Enable, 9-bit (RX9 Bit) ................................. 98 Receive Flag (RCIF Bit) ............................................. 20 Serial Port Enable (SPEN Bit) ............................. 97, 98 Single Receive Enable (SREN Bit) ............................ 98 Synchronous Master Mode ...................................... 107 Reception ........................................................ 109 Transmission ................................................... 108 Synchronous Slave Mode ........................................ 110 Transmit Data, 9th Bit (TX9D) ................................... 97 Transmit Enable (TXEN Bit) ...................................... 97 Transmit Enable (TXIE Bit) ........................................ 19 Transmit Enable, Nine-bit (TX9 Bit) ........................... 97 Transmit Flag (TXIE Bit) ............................................ 20 Transmit Shift Register Status (TRMT Bit) ................ 97 TXSTA Register ......................................................... 97 |
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