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MB9AF112LMA Datasheet(PDF) 5 Page - SPANSION |
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MB9AF112LMA Datasheet(HTML) 5 Page - SPANSION |
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5 / 121 page ![]() D a t a S h e e t 2 MB9A110A-DS706-00011-3v0-E, December 16, 2014 CONFIDENTIAL FEATURES 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Up to 512 Kbyte Read cycle: 0wait-cycle Security function for code protection [SRAM] This Series contain a total of up to 32Kbyte on-chip SRAM. On-chip SRAM is composed of two independent SRAM (SRAM0,SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max 8channels) 4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3) Operation mode is selectable from the followings for each channel. UART CSIO LIN I2C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)* Various error detection functions available (parity errors, framing errors, and overrun errors) * : MB9AF111LA, F312LA and F314LA do not support Hardware Flow control [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [LIN] LIN protocol Rev.2.1 supported Full-duplex double buffer Master/Slave mode supported LIN break field generation (can be changed 13-16bit length) LIN break delimiter generation (can be changed 1-4bit length) Various error detection functions available (parity errors, framing errors, and overrun errors) [I 2C] Standard-mode (Max 100kbps) / Fast-mode (Max 400Kbps) supported |
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