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MB9AF112LMA Datasheet(PDF) 85 Page - SPANSION |
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MB9AF112LMA Datasheet(HTML) 85 Page - SPANSION |
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85 / 121 page ![]() D a t a S h e e t 82 MB9A110A-DS706-00011-3v0-E, December 16, 2014 CONFIDENTIAL (9) CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Vcc < 4.5V Vcc ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Master mode 4tcycp - 4tcycp - ns SCK ↓ → SOT delay time tSLOVI SCKx SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tcycp - 10 - 2tcycp - 10 - ns Serial clock "H" pulse width tSHSL SCKx tcycp + 10 - tcycp + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx SINx 10 - 10 - ns SCK ↑→ SIN hold time tSHIXE SCKx SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: The above characteristics apply to CLK synchronous mode. t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance C L = 30pF. |
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