MB9AF112LMA datasheet(75/121 Pages) SPANSION

75 / 121 page

D a t a S h e e t

MB9A110A-DS706-00011-3v0-E, December 16, 2014

CONFIDENTIAL

(4-1) Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)

(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time

(LOCK UP time)*

tLOCK

100

μs

PLL input clock frequency

fPLLI

MHz

PLL multiple rate

multiple

PLL macro oscillation clock frequency

fPLLO

200

300

MHz

Main PLL clock frequency*

FCLKPLL

MHz

*1 : Time from when the PLL starts operating until the oscillation stabilizes.

*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

(4-2) Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the

input clock of the main PLL)

(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time

(LOCK UP time)*

tLOCK

100

μs

PLL input clock frequency

fPLLI

3.8

4.2

MHz

PLL multiple rate

multiple

PLL macro oscillation clock frequency

fPLLO

190

300

MHz

Main PLL clock frequency*

FCLKPLL

MHz

*1 : Time from when the PLL starts operating until the oscillation stabilizes.

*2 : For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family

PERIPHERAL MANUAL".

When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account

and prevent the master clock from exceeding the maximum frequency.

divider

PLL input

clock

Main

PLL

PLL macro

oscillation clock

divider

Main PLL

clock

(CLKPLL)

divider

Main PLL connection

High-speed CR clock (CLKHC)

Main clock (CLKMO)

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