| Electronic Components Datasheet Search |
|
MB9AF112LMA Datasheet(PDF) 77 Page - SPANSION |
|
|
|||||||||||||||||||||||||||||
MB9AF112LMA Datasheet(HTML) 77 Page - SPANSION |
|
77 / 121 page ![]() D a t a S h e e t 74 MB9A110A-DS706-00011-3v0-E, December 16, 2014 CONFIDENTIAL (7) External Bus Timing External bus clock output Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT Vcc ≥ 4.5 V - 40 MHz Vcc < 4.5 V - 32 MHz Minimum clock cycle time - Vcc ≥ 4.5 V 25 - ns Vcc < 4.5 V 31.25 - ns Note: The external bus clock output is a divided clock of HCLK. For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL" When external bus clock is not output, this characteristic does not give any effect on external bus operation. External bus signal input/output Characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH - 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH MCLKOUT Input signal Output signal |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |