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MB9AF112LMA Datasheet(PDF) 78 Page - SPANSION |
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MB9AF112LMA Datasheet(HTML) 78 Page - SPANSION |
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78 / 121 page  D a t a S h e e t December 16, 2014, MB9A110A-DS706-00011-3v0-E 75 CONFIDENTIAL Separate Bus Access Asynchronous SRAM Mode (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX Vcc ≥ 4.5V MCLK×n-3 - ns Vcc < 4.5V MCSX ↓→ Address output delay time tCSL – AV MCSX[7:0] MAD[24:0] Vcc ≥ 4.5V -9 + 9 ns Vcc < 4.5V -12 + 12 MOEX ↑ → Address hold time tOEH - AX MOEX MAD[24:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓→ MOEX ↓ delay time tCSL - OEL MOEX MCSX[7:0] Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX MDQM[1:0] Vcc ≥ 4.5V MCLK×m-9 MCLK×m+9 ns Vcc < 4.5V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX MADATA[15:0] Vcc ≥ 4.5V 20 - ns Vcc < 4.5V 38 - MOEX ↑ → Data hold time tDH - OE MOEX MADATA[15:0] Vcc ≥ 4.5V 0 - ns Vcc < 4.5V MWEX Min pulse width tWEW MWEX Vcc ≥ 4.5V MCLK×n-3 - ns Vcc < 4.5V MWEX ↑ → Address output delay time tWEH - AX MWEX MAD[24:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX MCSX[7:0] Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL-WDQML MCSX MDQM[1:0] Vcc ≥ 4.5V MCLK×n-9 MCLK×n+9 ns Vcc < 4.5V MCLK×n-12 MCLK×n+12 MCSX ↓ → Data output time tCSL - DV MCSX MADATA[15:0] Vcc ≥ 4.5V MCLK-9 MCLK+9 ns Vcc < 4.5V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX MADATA[15:0] Vcc ≥ 4.5V 0 MCLK×m+9 ns Vcc < 4.5V MCLK×m+12 Note: When the external load capacitance CL = 30pF (m = 0 to 15, n = 1 to 16). |
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