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PXA270 Datasheet(PDF) 29 Page - Intel Corporation

Part # PXA270
Description  Electrical, Mechanical, and Thermal Specification
PDF  126 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

PXA270 Datasheet(HTML) 29 Page - Intel Corporation

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Electrical, Mechanical, and Thermal Specification
4-9
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.2
Pin Usage
The pin usage summary shown in Table 4-1 does not include the 36 center balls identified as K10
through R15 (VF-BGA) or J9 through P14 (PBGA), all of which function as VSS_CORE (see the
recommendations for connecting the 36 center balls in the Intel® PXA27x Processor Family
Design Guide).
Each signal’s alternate function inputs are shown in the upper section of each signal row and the
outputs are shown in the lower section of each signal row. For example, GPIO<48> has a primary
input function of CIF_DD<5> and a secondary output function of nPOE.
Figure 4-8. 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)
VSS_CORE VSS_CORE VSS_CORE
VCC_LCD
GPIO[86]
VSS_IO
GPIO[87]
M
VSS_CORE VSS_CORE VSS_CORE
VSS_IO
GPIO[75]
GPIO[76]
GPIO[74]
N
VSS_CORE VSS_CORE VSS_CORE
VSS_CORE
GPIO[19]
GPIO[14]
GPIO[77]
TESTCLK
P
VCC_CORE
TCK
TMS
TDO
TDI
R
VSS_CORE
GPIO[4]
NTRST
CLK_REQ
GPIO[9]
T
VCC_CORE
NBATT_FAU
LT
GPIO[0]
GPIO[1]
GPIO[10]
U
VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL
NVDD_FAUL
T
SYS_EN
GPIO[3]
V
GPIO[50]
GPIO[106]
GPIO[104]
VCC_IO
GPIO[96]
PWR_CAP
[3]
VSS
PWR_OUT
NRESET
NRESET_O
UT
PWR_EN
W
GPIO[52]
GPIO[105]
GPIO[102]
GPIO[97]
GPIO[93]
VCC_BATT
PWR_CAP
[2]
PWR_CAP
[0]
VSS
TXTAL_IN TXTAL_OUT
Y
GPIO[53]
GPIO[108]
VSS_IO
GPIO[100]
GPIO[98]
GPIO[94]
VSS_IO
VSS_PLL
PXTAL_OUT
PWR_CAP
[1]
VSS
AA
GPIO[51]
GPIO[54]
GPIO[107]
GPIO[103]
GPIO[101]
GPIO[99]
GPIO[95]
VCC_PLL
PXTAL_IN
VSS
VSS
AB
12
13
14
15
16
17
18
19
20
21
22



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