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PXA270 Datasheet(PDF) 32 Page - Intel Corporation |
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PXA270 Datasheet(HTML) 32 Page - Intel Corporation |
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32 / 126 page  4-12 Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Pin Listing and Signal Definitions U4 T4 MD<5> ICOC Z MD<5> MD<5> — — Refer to Table 4-4 Y2 U3 MD<4> ICOC Z MD<4> MD<4> — — Refer to Table 4-4 Y3 Y1 MD<3> ICOC Z MD<3> MD<3> — — Refer to Table 4-4 AA3 U4 MD<2> ICOC Z MD<2> MD<2> — — Refer to Table 4-4 AB1 W3 MD<1> ICOC Z MD<1> MD<1> — — Refer to Table 4-4 AB4 W4 MD<0> ICOC Z MD<0> MD<0> — — Refer to Table 4-4 AC5 AA4 NOE OCZ nOE nOE — — Refer to Table 4-4 AB5 AA3 NWE OCZ nWE nWE — — Refer to Table 4-4 AC7 W6 NSDRAS OCZ nSDRAS nSDRAS — — Refer to Table 4-4 AA6 Y4 NSDCAS OCZ nSDCAS nSDCAS — — Refer to Table 4-4 AB9 W8 DQM<0> OCZ DQM<0> DQM<0> — — Refer to Table 4-4 AB10 AA7 DQM<1> OCZ DQM<1> DQM<1> — — Refer to Table 4-4 AC9 AB6 DQM<2> OCZ DQM<2> DQM<2> — — Refer to Table 4-4 AC10 AB7 DQM<3> OCZ DQM<3> DQM<3> — — Refer to Table 4-4 AB7 AA5 NSDCS<0 > OCZ nSDCS<0> nSDCS<0> — — Refer to Table 4-4 AB8 Y8 NSDCS<1 > OC nSDCS<1> nSDCS<1> — — Refer to Table 4-4 AD6 W7 SDCKE OC SDCKE SDCKE — — Refer to Table 4-4 AC4 AB3 SDCLK<0 > OC SDCLK<0> SDCLK<0> — — Refer to Table 4-4 AD7 AB5 SDCLK<1 > OCZ SDCLK<1> SDCLK<1> — — Refer to Table 4-4 AD3 AB4 SDCLK<2 > OC SDCLK<2> SDCLK<2> — — Refer to Table 4-4 C9 C8 RDNWR OCZ RDnWR RDnWR — — Refer to Table 4-4 B3 D6 NCS<0> OCZ nCS<0> nCS<0> — — Refer to Table 4-4 A3 A4 GPIO<15> ICOC Z GPIO<15> —— — Pu-1 Note[1] Note[4] nPCE<1> nCS<1> Refer to Table 4-4 — B9 D9 GPIO<18> ICOC Z GPIO<18> RDY — — Pd-0 Note[1] Note [3] —— — Table 4-1. Pin Usage Summary (Sheet 3 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function Secondary Alternate Function Third Alternate Function Reset State Sleep State NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. |
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