PXA270 datasheet(67/126 Pages) INTEL

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Electrical, Mechanical, and Thermal Specification

6-3

Intel® PXA270 Processor

AC Timing Specifications

5. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE,

VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be

established within 125 milliseconds of the assertion of PWR_EN.

6. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system

power supplies have been properly established.

7. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset

vector.

Note: nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor will not

begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and

PWR_DEL timers have expired. Refer to the Intel® PXA27x Processor Family Developer’s

Manual, “Initial Power On” and “Deep-Sleep Exit States” for a state diagram.

Figure 6-2. Power On Reset Timing

Table 6-2. Power-On Timing Specifications (Sheet 1 of 2)(OSCC[CRI] = 0)

Symbol

Description

Min

Typical

Max

Units

Delay from VCC_BATT assertion to

nRESET de-assertion

—

Delay from nRESET de-assertion to

SYS_EN assertion

—

101

—

Delay from SYS_EN assertion to

PWR_EN assertion

—

125

—

Power supply stabilization time (time to

the deassertion of nVDD_FAULT after the

assertion of PWR_EN)

—

120

Delay from the assertion of PWR_EN to

the de-assertion of nRESET_OUT

—

125

—

tbramp

VCC_BATT power-on Ramp Rate

—

mV/uS

VCC_USB, VCC_IO, VCC_MEM,

VCC_BB, VCC_LCD, VCC_USIM

VCC_CORE, VCC_SRAM,

VCC_PLL

nBATT_FAULT

nRESET

SYS_EN

PWR_EN

nVDD_FAULT

VCC_BATT

nRESET_OUT

tsysramp

tbramp

tpwrramp

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