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PXA270 Datasheet(PDF) 36 Page - Intel Corporation |
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PXA270 Datasheet(HTML) 36 Page - Intel Corporation |
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36 / 126 page  4-16 Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor Pin Listing and Signal Definitions N22 M20 GPIO<86> ICOC Z GPIO<86> SSPRXD2 LDD<16> USB_P3_5 Pd-0 Note[1] Note [3] nPCE<1> LDD<16> — N23 M22 GPIO<87> ICOC Z GPIO<87> nPCE<2> LDD<17> USB_P3_1 Pd-0 Note[1] Note [3] SSPTXD2 LDD<17> SSPSFRM2 VCC_IO C11 A8 GPIO<11> ICOC Z GPIO<11> EXT_SYNC<0> SSPRXD2 USB_P3_1 Pd-0 Note[1] Note [3], Note[11 CHOUT<0> PWM_OUT2 48_MHz B10 A7 GPIO<12> ICOC Z GPIO<12> EXT_SYNC<1> CIF_DD<7> — Pd-0 Note[1] Note [3], Note[11 CHOUT<1> PWM_OUT3 48_MHz C10 A6 GPIO<13> ICOC Z GPIO<13> CLK_EXT KP_DKIN<7> KP_MKIN< 7> Pd-0 Note[1] Note [3], Note[11] SSPTXD2 — — A18 C14 GPIO<16> ICOC Z GPIO<16> KP_MKIN<5> — — Pd-0 Note[1] Note [3] — PWM_OUT<0> FFTXD C16 D15 GPIO<17> ICOC Z GPIO<17> KP_MKIN<6> CIF_DD<6> — Pd-0 Note[1] Note [3] — PWM_OUT<1> — D13 A12 GPIO<22> ICOC Z GPIO<22> SSPEXTCLK2 SSPSCLKEN2 SSPSCLK2 Pd-0 Note[1] Note [3] KP_MKOUT<7> SSPSYSCLK2 SSPSCLK2 B16 A16 GPIO<23> ICOC Z GPIO<23> — SSPSCLK — Pd-0 Note[1] Note [3] CIF_MCLK SSPSCLK — A17 B14 GPIO<24> ICOC Z GPIO<24> CIF_FV SSPSFRM — Pd-0 Note[1] Note [3] CIF_FV SSPSFRM — D16 A15 GPIO<25> ICOC Z GPIO<25> CIF_LV — — Pd-0 Note[1] Note [3] CIF_LV SSPTXD — B15 A14 GPIO<26> ICOC Z GPIO<26> SSPRXD CIF_PCLK FFCTS Pd-0 Note[1] Note [3] —— — C15 C13 GPIO<27> ICOC Z GPIO<27> SSPEXTCLK SSPSCLKEN CIF_DD<0> Pd-0 Note[1] Note [3] SSPSYSCLK — FFRTS A14 D12 GPIO<28> ICOC Z GPIO<28> AC97_BITCLK I2S_BITCLK SSPSFRM Pd-0 Note[1] Note [3] I2S_BITCLK — SSPSFRM B13 A11 GPIO<29> ICOC Z GPIO<29> AC97_SDATA_I N_0 I2S_SDATA_IN SSPSCLK Pd-0 Note[1] Note [3] SSPRXD2 — SSPSCLK Table 4-1. Pin Usage Summary (Sheet 7 of 17) VF-BGA Ball# (13x13) PBGA Ball# (23x23) Name Type Function After Reset Primary Function Secondary Alternate Function Third Alternate Function Reset State Sleep State NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States. |
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