PXA270 datasheet(71/126 Pages) INTEL

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Electrical, Mechanical, and Thermal Specification

6-7

Intel® PXA270 Processor

AC Timing Specifications

Figure 6-5. Sleep Mode Timing

6.2.6

Deep-Sleep Mode Timing

Deep-sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.

Figure 6-6 and Table 6-7 show the required timing parameters for sleep mode. The timing

specifications listed are for software invoked (not battery or VDD fault) Deep-sleep entry, unless

specified.

Table 6-6. Sleep-Mode Timing Specifications

Symbol

Description

Min

Typical

Max3

Units

tentry5

Delay between MCR sleep command

issue to de-assertion of PWR_EN

0.56

—

2.51

msec

texit

Delay between wakeup event and run

mode

0.50

—

136.652,4

msec

tpwrdelay

Delay between assertion of PWR_EN to

PLL enable2

—

125

msec

NOTES:

1. -1mS if not using DC2DC and -0.94mS if any internal SRAM banks are not powered

2. 0.15ms less time if exiting from sleep mode to 13M mode

3. Add 0.1ms if the wake up event is external

4. Oscillator start/crystal stable times are programmable (300uS-11mS)

NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which

counts until the oscillator is stable. (Typical stabilization is 500

µs. Maximum can be upto 5ms)

5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode

SYS_EN

VCC_USB, VCC_IO,

VCC_BB,VCC_MEM,

VCC_LCD, VCC_USIM

PWR_EN

nVDD_FAULT

VCC_CORE, VCC_SRAM,

VCC_PLL

nRESET_OUT

(High)

(Enabled)

Wakeup Event

SLEEP(ENTRY)

SLEEP

SLEEP(EXIT)

NORMAL

Intel®PXA27x State:

Tentry

Texit

Tpwrdelay

PXA270 Datasheet(PDF) 71 Page - Intel Corporation

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