PXA270 datasheet(76/126 Pages) INTEL

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6-12

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

6.4

Memory and Expansion-Card Timing Specifications

Interfaces with the following memories must observe the AC timing requirements given in the

following subsections:

• Section 6.4.1, “Internal SRAM Read/Write Timing Specifications”

• Section 6.4.2, “SDRAM Parameters and Timing Diagrams”

• Section 6.4.3, “ROM Parameters and Timing Diagrams”

• Section 6.4.4, “Flash Memory Parameters and Timing Diagrams”

• Section 6.4.5, “SRAM Parameters and Timing Diagrams”

• Section 6.4.6, “Variable-Latency I/O Parameters and Timing Diagrams”

• Section 6.4.7, “Expansion-Card Interface Parameters and Timing Diagrams”

Note: The diagrams in this section use the following conventions:

• Input signals to the processor are represented using dashed waveforms.

• Outputs and bidirectional signals are represented using solid waveforms.

• Fixed parameters are shown using double arrows in grey (black and white print) or green

(color print).

• Programmable parameters are shown using bold single arrows.

• The processor register that is used to change a specific timing is given in the corresponding

timing table.

6.4.1

Internal SRAM Read/Write Timing Specifications

6.4.2

SDRAM Parameters and Timing Diagrams

Table 6-15 shows the timing parameters used in Figure 6-7. Also see Section 6.4.3 and Figure 6-11

for additional SDRAM bus tenure information. See Figure 6-10 for SDRAM fly-by bus tenures.

Table 6-14. SRAM Read/Write AC Specification

Symbols

Parameters

MIN

TYP

MAX

Units

tsramRD

4-beat read transfer

—

system bus

clocks

tsramWR

4-beat write transfer

—

system bus

clocks

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