PXA270 datasheet(69/126 Pages) INTEL

69 / 126 page

Electrical, Mechanical, and Thermal Specification

6-5

Intel® PXA270 Processor

AC Timing Specifications

6.2.3

Watchdog Reset Timing

Watchdog reset is generated internally and therefore has no external pin dependencies. The

nRESET_OUT pin is the only indicator of watchdog reset; it stays asserted for tDHW_OUT. The

timing is similar to that for GPIO reset — see Figure 6-4 for details.

6.2.4

GPIO Reset Timing

GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as

the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies

based on the selected clock frequency. If the clocks and power manager is in a frequency-change

sequence when GPIO reset is asserted (see Section 5.5.1, “32.768-kHz Oscillator Specifications”

on page 5-9.), then Figure 6-4 shows the timing of GPIO reset, and Table 6-5 shows the GPIO reset

timing specifications.

Note: When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is

not asserted during GPIO reset. For register details, see the “Clocks and Power Manager” chapter

in the Intel® PXA27x Processor Family Developer’s Manual.

Table 6-4. Hardware Reset Timing Specifications (OSCC[CRI] = 1)

Symbol

Description

Min

Typical

Max

Units

Delay between nRESET asserted and

nRESET_OUT asserted

—

< 100 ns

Assertion time of nRESET

—

Delay between nRESET de-asserted and

nRESET_OUT de-asserted

2256

—

3265

Figure 6-4. GPIO Reset Timing

GP[1]

nRESET_OUT

nCS0

tA_GPIO<1>

tDHW_OUT_A

tDHW_OUT

tCS0

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