DP83266 datasheet(29/152 Pages) NSC

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60 Functional Description (Service Engine) (Continued)

The MACSI device provides the ability to group incoming

frames and then generate interrupts (via attentions) at

group boundaries To group incoming frames the MACSI

device defines status breakpoints which identify the end of

a group (burst) of related frames Status breakpoints can be

enabled to generate an attention

The breakpoints for Indicate Channels are defined by the

host in the Indicate Mode Indicate Notify and Indicate

Threshold registers Status breakpoints include Channel

change receipt of a token SA change DA change MAC

Info change or a user-specified number of frames have

been copied on a particular Indicate Channel

Status breakpoint generation may be individually enabled

for Indicate Channels 1 and 2 by setting the corresponding

Breakpoint bits (Breakpoint on Burst End Breakpoint on

Service Opportunity and Breakpoint on Threshold) in the

Indicate Mode Register and enabling the breakpoints to

generate an attention by setting the corresponding Break-

point bit in the Indicate Notify Register

When an Indicate exception occurs the current frame is

marked complete status is written into an IDUDLast and

the Channel’s Exception (EXC) bit in the Indicate Attention

When an Indicate error (other than a parity error) is detect-

ed the Error (ERR) bit in the State Attention Register is set

The host must reset the INSTOP Attention bit to restart pro-

cessing

When parity checking is enabled and a parity error is detect-

ed in a received frame it is recorded in the Indicate Status

field of the IDUD and the Ring Engine Parity Error (REPE)

bit in the Status Attention Register is set

A frame which is stripped after the fourth byte of the Infor-

mation Field (this may occur because an upstream station

detected an error within the frame) will be copied to memory

but the status will show that the frame was stripped

622 Request Operation

The Request Block transmits frames from host memory to

the Ring Engine Data is presented to the Ring Engine as a

byte stream

The Request Block performs the following functions

Prioritizes active requests to transmit frames

Requests the Ring Engine to obtain a token

Transmits frames to the Ring Engine

Writes status for transmitted and returning frames

Issues interrupts to the host on user-defined group

boundaries

The Request Machine processes requests by first reading

Request Descriptors from the REQ Queue and then assem-

bling frames of the specified service class Frame Control

(FC) and expected status for transmission to the Ring En-

gine Request and ODUD Descriptors are checked for con-

sistency and the Request Class is checked for compatibility

with the current ring state When an inconsistency or incom-

patibility is detected the request is aborted

When a consistency failure occurs the Request is terminat-

ed and a Confirmation Descriptor (CNF) with the appropriate

status is generated The Request Machine then locates the

end of the current object (REQ or ODUD) If the current

Descriptor is not the end (Last bit not set) the Request

Machine will fetch subsequent Descriptors until it detects

the end and then resume processing with the next Descrip-

torFirst or DescriptorOnly

Requests are processed on both Request Channels simul-

taneously Their interaction is determined by their priorities

(Request Channel 0 has higher priority than Request Chan-

nel 1) and the Hold and PreemptPrestage bits in the Re-

quest Channel’s Request Configuration Register An active

Request Channel 0 is always serviced first and may be pro-

grammed to preempt Request Channel 1 such that uncom-

mitted Request Channel 1’s data already in the request

FIFO will be purged and then refetched after servicing Re-

quest Channel 0 When prestaging is enabled the next

frame is staged before the token arrives Prestaging is al-

ways enabled for Request Channel 0 and is a programma-

ble option on Request Channel 1 The MACSI device will

process at most one Request per Channel per Service Op-

portunity

The MACSI device contains an option bit which controls the

timing of Token capture This bit is the Early Token Request

bit (ETR) which is in R0CR1 (for Request Channel 0) and

R1CR1 (for Request Channel 1) When the ETR bit is dis-

abled for a channel the MACSI device will fetch a Request

descriptor and then fetch the first ODUD and begin filling

the transmit FIFO for that channel When the FIFO thresh-

old is reached (R0CR0TT or R1CR0TT) the MACSI device

presents a Request Class to the Ring Engine which causes

the Ring Engine to capture a Token of the specified class

When the ETR bit is enabled a REQFirst is loaded the

Request Machine commands the Ring Engine to capture a

token of the type specified in the REQ Descriptor and con-

currently fetches the first ODUD This mode is useful for

systems which need tight control of the Token capture tim-

ing (eg systems using Synchronous traffic) Note that use

of the Early Token Request mechanism may under certain

circumstances waste ring bandwidth (ie

holding the To-

ken while filling the FIFO) Therefore it should be enabled

only in those systems where the feature is specifically re-

quired

If prestaging is enabled or a Service Opportunity exists for

this Request Channel data from the first ODU is loaded into

the Request FIFO and the MACSI device requests trans-

mission from the Ring Engine When the Ring Engine has

captured the appropriate token and the frame is committed

to transmission (the FIFO threshold has been reached or

the end of the frame is in the FIFO) transmission begins

The MACSI device fetches the next ODUD and starts load-

ing the ODUs of the next frame into the FIFO This contin-

ues (across multiple service opportunities if required) until

all frames for that Request have been transmitted (ie an

REQONLY or an REQLAST is detected) or an exception or

error occurs which prematurely ends the Request

The MACSI device will load REQ Descriptors as long as the

RQSTOP bit in the State Attention Register is Zero the

REQ Queue contains valid entries (the REQ Queue Pointer

and there is space in the CNF Queue (the MACSI device

has not detected equality of the CNF Queue Pointer Regis-

ter and the CNF Queue Limit Register)

DP83266 Datasheet(PDF) 29 Page - National Semiconductor (TI)

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