DP83266 datasheet(35/152 Pages) NSC

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60 Functional Description (Service Engine) (Continued)

Master States

The Ti state exists when no bus activity is required The BIU

does not drive any of the bus signals when it is in this state

(all are released) If the BIU requires bus service it may

assert Bus Request

When a transaction occurs the BIU enters Tbr asserts Bus

Request and then waits for Bus Grant to be asserted

The state following Tbr is either Tva or Tpa In Virtual Ad-

dress Mode the BIU enters Tva and drives the virtual ad-

dress and size lines onto the bus In Physical Address

Mode Tpa occurs next (see Section 643)

Following a Tva state is a Tmmu state During this cycle the

external MMU is performing a translation of the virtual ad-

dress emitted during Tva

Following a Tmmu state (when using virtual addressing) or a

Tbr state (when using physical addressing) is the Tpa state

During the Tpa state the MACSI device drives the read

write strobes and size signals In physical address mode it

also drives AB

AD with address In virtual address mode

the MACSI device TRI-STATEs AB

BD so the host CPU or

MMU can drive the address

Following the Tpa state the BIU enters the Td state to

transfer data words Each data transfer may be extended

indefinitely by inserting Tw states A slave acknowledges by

asserting AB

ACK and transferring data in a Td state (cy-

cle) If the slave can drive data at the rate of one word per

clock (in a burst) it keeps AB

ACK asserted

Following the final TdTw state the BIU enters a Tr state to

allow time to turn off or turn around bus transceivers

A bus retry request is recognized in any TdTw state The

BIU will go to a Tr state and then rerun the transaction when

it obtains a new Bus Grant The whole transaction is retried

ie all words of a burst Additionally no other transaction

will be attempted before the interrupted one is retried The

BIU retries indefinitely until either the transaction completes

successfully or a bus error is signaled

Bus errors are recognized in TdTw states

643 Physical Addressing Bus Transactions

Bus transactions in Physical Address Mode are shown in

Figure 6-4 through Figure 6-7 MACSI device signals are

defined in Section 8

TLF11705 – 9

FIGURE 6-4 ABus Single Read Physical Addressing0 ws 1 ws

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