DP83266 datasheet(31/152 Pages) NSC

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60 Functional Description (Service Engine) (Continued)

TLF11705 – 8

FIGURE 6-2 MACSI Device External Matching Interface Timing

Note that this design allows ECIP to be a positive or nega-

tive pulse To confirm frames in this mode (typically with

Source Address Transparency enabled) EM must be as-

serted within the same timeframe as ECOPY

The Ring Engine samples EA two byte-times after the end

delimiter (ED) is passed between the PLAYERa device and

the MACSI device If EA is asserted the MACSI device will

transmit the A Indicator as an S The Ring Engine samples

EM continuously and will begin to strip a frame three byte-

times after the assertion of EM This implies that the user

must ground EM if not used The Ring Engine does not use

the ECIP timing signal

It is important to note that ECIP functions as an indicator to

the internal MACSI device Indicate Machine to hold off the

copying of incoming data until the ECIP line is negated

Therefore even if a design does not intend to take advan-

tage of the MACSI device External Address Matching inter-

face the user must still ensure that the ECIP signal line is

properly negated Also important is the fact that the MACSI

device samples the ECIP signal line in order to detect just

two conditions It looks at whether ECIP is asserted at any

time during the period between the start delimiter (JK) and

the 6th byte of the INFO field and then waits until the deas-

sertion of ECIP at which point the MACSI device samples

the ECOPY and EM signal lines for their status on this par-

ticular frame

In the timing diagram (see

Figure 6-2 ) the specific cycles

shown for the assertion and deassertion of ECIP comprise

only one possible valid timing Other timings are valid as

well within the limits of the timing parameters to be de-

scribed below Shaded areas indicate cycles where the

MACSI device is not sampling the signal lines for this partic-

ular pattern Note that the sampling of ECIP is level sensi-

tive and synchronous with LBC1

Note that there are five timing parameters (T1 – T5) T1 and

T3 are limits as to when the initial assertion of ECIP will be

recognized Once ECIP is asserted T2 T4 and T5 become

timing limits on the deassertion of ECIP Once deasserted

ECIP is not sampled further (until the start of the next

frame)

T1 is the earliest cycle where the assertion of ECIP will be

recognized ECIP may be asserted earlier than this but the

MACSI device will not sample it during these earlier periods

T1’s timing is fixed as the fourth cycle following the FC data

byte at the PLAYERa MACSI interface

T2 is the earliest cycle where the deassertion of ECIP will be

recognized This can occur as soon as one cycle following

ECIP’s assertion ECIP needs to be asserted for a minimum

of one full clock cycle

T3 is the latest cycle where the initial assertion of ECIP will

still be recognized T3 must occur before the 6th byte of the

INFO field not afterward If ECIP is asserted later than this

cycle an external match will not be recognized ie

the

frame will be copied only if it is an internal match When

ECIP is not asserted until after T3 it is not recognized This

is the only case where maintaining ECIP’s assertion during

the frame will have no effect at all

T4 is the latest cycle where the deassertion of ECIP will be

recognized in ‘‘regular’’ fashion That is if ECIP is held as-

serted beyond T4 a special case is created within the MAC-

SI device when the external compare has persisted to the

point where it takes precedence over all other copy modes

In this case all frames which are copied regardless of

whether it was an external match internal match or SMT

frame are copied to ICHN2 Note that even if an internal

match has already occurred ECIP must still become deas-

serted for the frame copy to complete

It is important to note that the timing shown for T4 is depen-

dent on the setting of the SMLB bit of the MACSI device’s

System Interface Mode Register 0 (SIMR0) The timing

shown in

Figure 6-2 is for frame copies in small-burst mode

only T4 signifies the boundary condition internal to the

MACSI device where the first full burst of data has been

received The ABus write access for this data will then auto-

matically default to ICHN2 if an external copy decision is still

pending regardless of sort mode When the SMLB bit is

not set ie in large burst mode T4 would occur 16 cycles

later than shown in

Figure 6-2

T5 is the final cycle where the deassertion of ECIP can be

recognized and it occurs two cycles after the end delimiter

(ED) is transferred between the PLAYERa and MACSI de-

vices If ECIP is held high beyond this point the frame will

not be copied at all even if an internal match occurred

Note that this is true even if InternalExternal sorting is not

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