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DP83266 Datasheet(PDF) 56 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 56 Page - National Semiconductor (TI) |
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56 / 152 page ![]() 70 Control Information (Continued) Function Register (Function) The Ring Engine performs the MAC Reset Claim Request and Beacon Request using the Function Register The Register is initialized to Zero after a master reset A function is performed by setting the appropriate bit to One When the function is complete the bit is cleared by the Ring Engine Access Rules Address Read Write 002h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES RES RES CLM BCN MCRST RES MARST Bit Symbol Description D7 – D5 RES Reserved D4 CLM Claim Request Produces the functions equivalent to an SM CONTROLrequest (Claim) and causes entry to the Tx Claim State The Ring Engine Transmitter is forced to enter the Tx Claim State unless the Transmitter is in the Tx Beacon State or bit BCN is set to One Claim frames are then transmitted until the Claim process completes The Claim process will not complete if OptionITR e 1 A Claim Request is honored immediately from any state except the Beacon state It is honored in the Beacon state when a My Beacon returns Claim requests are honored even when OptionIRR e 1 Claim frames are generated by the Ring Engine unless an Immediate Claim Request is available at the MAC Request Interface Even with an Immediate Claim Request at the Interface the Ring Engine transmits at least one Claim frame before the Claim frames from the MAC Request Interface are transmitted If an external Claim frame is to be transmitted the Claim frame should first be set up then the request should be given to the MAC Request Interface before the CLM bit is set to One The CLM bit is reset upon entry to the Claim or Beacon state D3 BCN Beacon Request Produces the functions of an SM CONTROLrequest (Beacon) as required by the FDDI MAC Standard The Ring Engine Transmitter is forced to enter the Tx Beacon State Beacon frames are then transmitted until the Tx Beacon Process completes The Beacon Process will not complete if OptionIRR e 1 Beacon frames are generated by the Ring Engine unless an Immediate Beacon Request is present at the MAC Request Interface and a frame is ready to be transmitted Even with an External Immediate Beacon Request the Ring Engine transmits at least one Beacon frame before the Beacon frames from the MAC Request Interface are transmitted If an external Beacon frame is to be transmitted the Beacon frame should first be set up via the System Interface and then bit BCN should be set to One Setting this bit also sets bit D2 (MCRST) The BCN bit is cleared on entry to the Beacon state If the User programs both D3 (BCN) and D4 (CLM) simultaneously bit D3 (BCN) takes precedence D2 MCRST MAC Reset Forces the Receiver to state R0 (Listen) and the Transmitter to state T0 (Idle) TNEG (Registers 098 – 09B) is not loaded with TMAX (this operation can be performed as part of the MAC Reset Request actions by writing to TNEG Timers before the MAC Reset is initiated) MCRST takes precedence over bits D3 (BCN) and D4 (CLM) but does not clear these bits A MAC Reset that occurs while a frame is being transmitted will cause the frame to be aborted Frames without the Frame Status are not transmitted by the Ring Engine Whenever the byte with the Ending Delimiter is transmitted valid frame status is transmitted as well If a MAC Reset occurs during the byte where the Ending Delimiter and E Indicator should be transmitted it will not be transmitted If a MAC Reset occurs on the cycle where the A and C Indicators are transmitted they will still be transmitted D1 RES Reserved D0 MARST Master Reset A Master Reset is functionally equivalent to a hardware reset of the Ring Engine (MAC) A Master Reset sets all Ring Engine state machines and registers to default values Master Reset causes the MCRST bit to be set It also clears the Mode Option Event and Mask Registers The Timers are set to their defaults The Counters are not cleared When the Master Reset function is complete bit D0 (MARST) is set to Zero At this time all bits in the Function Register should be Zero 56 |
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