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DP83266 Datasheet(PDF) 65 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 65 Page - National Semiconductor (TI) |
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65 / 152 page ![]() 70 Control Information (Continued) Token and Timer Event Mask Register 0 (TEMR0) The Token and Timer Event Mask Register 0 (TEMR0) is used to mask bits in Register TELR0 If a bit in Register TEMR0 is set to One the corresponding bit in Register TELR will be applied to the Interrupt Condition Register which can then be used to generate an interrupt All bits in this register are set to Zero upon reset Access Rules Address Read Write 015h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Bit Symbol Description D7 RLVD Ring Latency Valid Mask This bit is used to mask TELR0RLVD D6 TKPASS Token Passed Mask This bit is used to mask TELR0TKPASS D5 TKCAPT Token Captured Mask This bit is used to mask TELR0TKCAPT D4 CBERR ClaimBeacon Error Mask This bit is used to mask TELR0CBERR D3 DUPTKR Duplicated Token Received Mask This bit is used to mask TELR0DUPTKR D2 TRTEXP TRT Expired and Set Late Flag Mask This bit is used to mask TELR0TRTEXP D1 TVXEXP TVX Expired Mask This bit is used to mask TELR0TVXEXP D0 ENTRMD Enter Restricted Mode Mask This bit is used to mask TELR0ENTRMD 65 |
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