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DP83266 Datasheet(PDF) 108 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 108 Page - National Semiconductor (TI) |
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108 / 152 page ![]() 70 Control Information (Continued) Indicate Attention Register (IAR) The Indicate Attention Register (IAR) is used to present exception and breakpoint attentions generated by each Indicate Channel An Attention bit is set by hardware when an exception or breakpoint occurs on the corresponding Indicate Channel Each bit may be enabled by setting the corresponding bit in the Indicate Notify Register All bits in this register are set to Zero upon reset Access Rules Address Read Write 114h Always Conditional Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES RES EXCI0 BRKI0 EXCI1 BRKI1 EXCI2 BRKI2 Bit Symbol Description D0 BRKI2 Breakpoint on ICHN2 This bit is set when a breakpoint is detected on Indicate Channel 2 No action is taken if the host sets this bit D1 EXCI2 Exception on ICHN2 While this bit is set copying is disabled on ICHN2 This bit is set by the MACSI device when an exception occurs on Indicate Channel 2 An exception consists of an ABus error during an IDU or IDUD write for ICNH2 It may be set by the host to disable copying on ICHN2 which is convenient when updating the Indicate Header Length and Indicate Threshold register When this bit is set by the device it signifies that the last frame received on this channel had an ABus error It is the last frame because the setting of this bit disables further copying on this channel The last frame should be discarded D2 BRKI1 Breakpoint on ICHN1 This bit is set when a breakpoint is detected on Indicate Channel 1 No action is taken if the host sets this bit D3 EXCI1 Exception on ICHN1 While this bit is set copying is disabled on ICHN1 This bit is set by the MACSI device when an exception occurs on Indicate Channel 1 An exception consists of an ABus error during an IDU or IDUD write for ICNH1 It may be set by the host to disable copying on ICHN1 which is convenient when updating the Indicate Header Length and Indicate Threshold register When this bit is set by the device it signifies that the last frame received on this channel had an ABus error It is the last frame because the setting of this bit disables further copying on this channel The last frame should be discarded D4 BRKI0 Breakpoint on ICHN0 This bit is set when a breakpoint is detected on ICHN0 No action is taken if the host sets this bit The User must set IMCRBOS to use the BRKI0 breakpoint D5 EXCI0 Exception on ICHN0 While this bit is set copying is disabled on ICHN0 This bit is set by the MACSI device when an exception occurs on Indicate Channel 0 An exception consists of an ABus error during an IDU or IDUD write for ICNH0 It may be set by the host to disable copying on ICHN0 When this bit is set by the device it signifies that the last frame received on this channel had an ABus error It is the last frame because the setting of this bit disables further copying on this channel The last frame should be discarded D7 – D6 RES Reserved 108 |
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