DAC7760IPWPR datasheet(31/63 Pages) TI1

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Supply (V)

Specified Supply

Voltage Range

No Power-On Reset

Supply Max.

Supply Min.

Power-On Reset

POR Threshold

Undefined

Undefined Operation Threshold

DAC7760, DAC8760

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SBAS528B – JUNE 2013 – REVISED JUNE 2016

Product Folder Links: DAC7760 DAC8760

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Figure 85. Relevant Voltage Levels for POR Circuit

For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V

(supply maximum). For the DVDD supply region between 2.4 V (undefined operation threshold) and 0.8 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the

DVDD supply below 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is below 0.8 V

for approximately 1 ms.

For the AVDD supply, no internal POR occurs for nominal supply operation from 10 V (supply minimum) to 36 V

(supply maximum). For AVDD supply voltages between 8 V (undefined operation threshold) to 1 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the

AVDD supply below 1 V (POR threshold), the internal POR resets as long as the supply voltage is below 1 V for

approximately 1 ms. In case the DVDD or AVDD supply drops to a level where the internal POR signal is

indeterminate, either power cycle the device or toggle the LATCH pin followed by a software reset. Both options

initialize the internal circuitry to a known state and provide proper operation.

8.3.9 Alarm Detection

The device also provides an alarm detection feature. When one or more of following events occur, the ALARM

pin goes low:

•

The current output load is in open circuit; or

•

The voltage at IOUT reaches a level where the accuracy of the output current is compromised. This condition

is detected by monitoring internal voltage levels of the IOUT circuitry and is typically below the specified

compliance voltage headroom (defined as the voltage drop between the AVDD and IOUT pins) minimum of 2

V; or

•

The die temperature has exceeded 142°C; or

•

The SPI watchdog timer exceeded the timeout period (if enabled); or

•

The SPI frame error CRC check encountered an error (if enabled).

When the ALARM pins of multiple DACx760 devices are connected together to form a wired-AND function, the

host processor must read the status register of each device to know all the fault conditions that are present. Note

that the thermal alarm has hysteresis of about 18°C. After being set, the alarm only resets when the die

temperature drops below 124°C.

8.3.10 Watchdog Timer

This feature is useful to make sure that communication between the host processor and the DACx760 has not

been lost. It can be enabled by setting the WDEN bit of the Configuration Register to 1. The watchdog timeout

period can be set using the WDPD bits of the configuration register, as shown in Table 3. The timer period is

based off an internal oscillator with a typical value of 8 MHz.

DAC7760IPWPR Datasheet(PDF) 31 Page - Texas Instruments

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