DAC7760IPWPR datasheet(40/63 Pages) TI1

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DAC7760, DAC8760

SBAS528B – JUNE 2013 – REVISED JUNE 2016

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Table 16. Command and Register Map (continued)

COMMAND

READ/WRITE

ACCESS

DATA BITS (DB15:DB0)

10:9

DAC Gain

Calibration

(2)

G15:G0, unsigned

DAC Zero Calibration

(2)

Z15:Z0, signed

Watchdog Timer

(3)

—

8.6.1.1 DACx760 Register Descriptions

8.6.1.1.1

Control Register

The DACx760 control register is written to at address 0x55. Table 17 shows the description for the control

Table 17. Control Register 0x55

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15

CLRSEL

VOUT clear value select bit.

When bit = 0, VOUT is 0 V in DAC Clear mode or after reset.

When bit = 1, VOUT is midscale in unipolar output and negative-full-scale in bipolar output

in DAC Clear mode or after reset.

DB14

OVR

Setting the bit increases the voltage output range by 10%.

DB13

REXT

External current setting resistor enable.

DB12

OUTEN

Output enable.

Bit = 1: Output is determined by RANGE bits.

Bit = 0: Output is disabled. IOUT and VOUT are Hi-Z.

DB11:DB8

SRCLK[3:0]

0000

Slew rate clock control. Ignored when bit SREN = 0

DB7:DB5

SRSTEP[2:0]

000

Slew rate step size control. Ignored when bit SREN = 0

DB4

SREN

Slew Rate Enable.

Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is

determined by SRCLK and SRSTEP.

Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output

changes to the new level immediately.

DB3

DCEN

Daisy-chain enable.

DB2:DB0

RANGE[2:0]

000

Output range bits.

8.6.1.1.2

Configuration Register

The DACx760 configuration register is written to at address 0x57. Table 18 summarizes the description for the

configuration register bits.

Table 18. Configuration Register 0x57

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB11

Reserved. User must not write any value other than zero to these bits.

DB10:DB9

IOUT RANGE

IOUT range. These bits are only used if both voltage and current outputs are

simultaneously enabled through bit 8 (DUAL OUTEN). The voltage output

range is still controlled by bits 2:0 of the Control Register (RANGE bits). The

current range is controlled by these bits and has similar behavior to

RANGE[1:0] when RANGE[2] = 1. However, unlike the RANGE bits, a change

to this field does not make the DAC data register go to its default value.

DB8

DUAL OUTEN

DAC dual output enable. This bit controls if the voltage and current outputs are

enabled simultaneously. Both are enabled when this bit is high. However, both

outputs are controlled by the same DAC data register.

DB7

APD

Alternate power down. On power-up, +VSENSE is connected to the internal

VOUT amplifier inverting terminal. Diodes exist at this node to REFIN and

GND. Setting this bit connects this node to ground through a resistor. When

set, the equivalent resistance seen from +VSENSE to GND is 70 kΩ. This is

useful in applications where the VOUT and IOUT terminals are tied together.

DB6

Reserved. Do not write any value other than zero to these bits.

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