DAC7760IPWPR datasheet(41/63 Pages) TI1

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DAC7760, DAC8760

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SBAS528B – JUNE 2013 – REVISED JUNE 2016

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Table 18. Configuration Register 0x57 (continued)

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB5

CALEN

User calibration enable. When user calibration is enabled, the DAC data are

adjusted according to the contents of the gain and zero calibration registers.

See User Calibration.

DB4

HARTEN

Enable interface through HART-IN pin (only valid for IOUT set to 4-mA to 20-

mA range through RANGE bits).

Bit = 1: HART signal is connected through internal resistor and modulates

output current.

Bit = 0: HART interface is disabled.

DB3

CRCEN

Enable frame error checking.

DB2

WDEN

Watchdog timer enable.

DB1:DB0

WDPD[1:0]

Watchdog timeout period.

8.6.1.1.3

DAC Registers

The DAC registers consist of a DAC data register (Table 19), a DAC gain calibration register (Table 20), and a

DAC zero calibration register (Table 21). User calibration as described in User Calibration is a feature that allows

for trimming the system gain and zero errors. Table 19 through Table 21 show the DAC8760, 16-bit version of

these registers. The DAC7760 (12-bit version) register contents are located in DB15:DB4. For DAC7760,

DB3:DB0 are don't care bits when writing and zeros when reading.

Table 19. DAC Data Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

D15:D0

0000h

DAC data register. Format is unsigned straight binary.

Table 20. DAC Gain Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

G15:G0

0000h

Voltage and current gain calibration register for user calibration. Format is

unsigned straight binary.

Table 21. DAC Zero Calibration Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

Z15:Z0

0000h

Voltage and current zero calibration register for user calibration. Format is twos

complement.

8.6.1.1.4

Reset Register

The DACx760 reset register is written to at address 0x56. Table 22 provides the description.

Table 22. Reset Register 0x56

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB1

0000h

Reserved. Writing to these bits does not cause any change.

DB0

RESET

Software reset bit. Writing 1 to the bit performs a software reset to reset all

registers and the ALARM status to the respective power-on reset default value.

After reset completes the RESET bit clears itself.

8.6.1.1.5

Status Register

This read-only register consists of four ALARM status bits (CRC-FLT, WD-FLT, I-FLT, and T-FLT) and bit SR-ON

that shows the slew rate status.

The device continuously monitors the output and die temperature. When an alarm occurs, the corresponding

ALARM status bit is set (1). Whenever an ALARM status bit is set, it remains set until the event that caused it is

resolved. The ALARM bit can only be cleared by performing a software reset, or a power-on reset (by cycling

power), or having the error condition resolved. These bits are reasserted if the ALARM condition continues to

exist in the next monitoring cycle.

DAC7760IPWPR Datasheet(PDF) 41 Page - Texas Instruments

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