DAC7760IPWPR datasheet(32/63 Pages) TI1

32 / 63 page

DAC7760, DAC8760

SBAS528B – JUNE 2013 – REVISED JUNE 2016

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Table 3. Watchdog Timeout Period

WDPD BITS

WATCHDOG TIMEOUT PERIOD (Typical, ms)

10 ms

51 ms

102 ms

204 ms

If enabled, the chip must have an SPI frame with 0x95 as the write address byte written to the device within the

programmed timeout period. Otherwise, the ALARM pin asserts low and the WD-FLT bit of the status register is

set to 1. Note that the ALARM pin can be asserted low for any of the different conditions as explained in the

Alarm Detection section. The WD-FLT bit is reset to 0 with a software reset, or by disabling the watchdog timer,

or by powering down the device.

When using multiple DACx760 devices in a daisy-chain configuration, the open-drain ALARM pins of all devices

can be connected together in a wired-AND function. The watchdog timer can be enabled in any number of the

devices in the chain although enabling it in one device is sufficient. The wired-AND ALARM pin may get pulled

low because of the simultaneous presence of different trigger conditions in the daisy-chained devices. The host

processor must read the status register of each device to know all the fault conditions present in the chain.

8.3.11 Frame Error Checking

If the DACx760 is used in a noisy environment, error checking can be used to check the integrity of SPI data

communication between the device and the host processor. This feature can be enabled by setting the CRCEN

bit of the Configuration Register to 1. The frame error checking scheme is based on the CRC-8-ATM (HEC)

polynomial x8 + x2 + x + 1 (that is, 100000111). When error checking is enabled, the SPI frame width is 32 bits,

as shown in Table 4. Start with the default 24-bit frame and enable frame error checking through the CRCEN bit

and switch to the 32-bit frame. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the

host processor before feeding it to the device. For a register readback, the CRC polynomial is output on the SDO

pins by the device as part of the 32-bit frame.

Table 4. SPI Frame With Frame Error Checking

Enabled

BIT 31:BIT 8

BIT 7:BIT 0

Normal SPI frame data

8-bit CRC polynomial

The DACx760 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the frame,

the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or multiple-bit

errors), the ALARM pin asserts low and the CRC-FLT bit of the status register is also set to 1. Note that the

ALARM pin can be asserted low for any of the different conditions as explained in Alarm Detection. The CRC-

FLT bit is reset to 0 with a software reset, or by disabling the frame error checking, or by powering down the

device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.

Frame error checking can be enabled for any number of DACx760 devices connected in a daisy-chain

configuration. However, TI recommends enabling error checking for none or all devices in the chain. When

connecting the ALARM pins of all combined devices, forming a wired-AND function, the host processor must

read the status register of each device to know all the fault conditions present in the chain. For proper operation,

the host processor must provide the correct number of SCLK cycles in each frame, taking care to identify

whether or not error checking is enabled in each device in the daisy-chain.

8.3.12 User Calibration

The device implements a user-calibration function to allow for trimming the system gain and zero errors. There is

a gain calibration register and a zero calibration register; the DAC output is calibrated according to the value of

these registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The gain

of the register is 0x0000, which is equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768

LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input

data format of the zero register is twos complement. The gain and offset calibration is described by Equation 6.

DAC7760IPWPR Datasheet(PDF) 32 Page - Texas Instruments

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