DAC7760IPWPR datasheet(38/63 Pages) TI1

38 / 63 page

DAC7760, DAC8760

SBAS528B – JUNE 2013 – REVISED JUNE 2016

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Table 12. Default SPI Frame

BIT 23:BIT 16

BIT 15:BIT 0

Address byte

Data word

The host processor must issue 24 bits before it issues a rising edge on the LATCH pin. Input data bits are

clocked in regardless of the LATCH pin and are unconditionally latched on the rising edge of LATCH. By default,

the SPI shift register resets to 000000h at power on or after a reset.

8.5.1.2 Write Operation

A write operation is accomplished when the address byte is set according to Table 13. For more information on

the DACx760 registers, see DACx760 Commands and Register Map.

Table 13. Write Address Functions

ADDRESS BYTE

FUNCTION

0x00

No operation (NOP)

0x01

Write DAC Data register

0x02

0x55

Write control register

0x56

Write reset register

0x57

Write configuration register

0x58

Write DAC gain calibration register

0x59

Write DAC zero calibration register

0x95

Watchdog timer reset

8.5.1.3 Read Operation

A read operation is accomplished when the address byte is 0x02. Follow the read operation with a no-operation

(NOP) command to clock out an addressed register, as shown in Figure 2. To read from a register, the address

byte and data word is as shown in Table 14. The read register value is output MSB first on SDO on successive

falling edges of SCLK.

Table 14. Default SPI Frame for Register Read

ADDRESS BYTE

DATA WORD

BIT 15:BIT 6

BIT 5:BIT 0

0x02

X (don't care)

Table 15 shows the register read addresses available on the DACx760 devices.

(1)

X denotes don't care bits.

Table 15. Register Read Address Functions

READ ADDRESS(1)

FUNCTION

XX XX00

Read status register

XX XX01

Read DAC data register

XX XX10

Read control register

00 1011

Read configuration register

01 0011

Read DAC gain calibration register

01 0111

Read DAC zero calibration register

8.5.1.4 Stand-Alone Operation

SCLK can operate in either continuous or burst mode as long as the LATCH rising edge occurs after the

appropriate number of SCLK cycles. Providing more than or less than 24 SCLK cycles before the rising edge of

LATCH results in incorrect data being programmed into the device registers and incorrect data sent out on SDO.

The rising edge of SCLK that clocks in the MSB of the 24-bit input frame marks the beginning of the write cycle,

and data are written to the addressed registers on the rising edge of LATCH.

DAC7760IPWPR Datasheet(PDF) 38 Page - Texas Instruments

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