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DAC7760IPWPR Datasheet(PDF) 36 Page - Texas Instruments

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Part # DAC7760IPWPR
Description  Single-Channel, 12- and 16-Bit Programmable Current Output and Voltage Output Digital-to-Analog Converters for 4-mA to 20-mA Current Loop Applications
PDF  63 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC7760IPWPR Datasheet(HTML) 36 Page - Texas Instruments

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25
Time (200 µs/div)
no cap
3 nF CAP1
3 nF CAP2
10 nF CAP1
10 nF CAP2
C001
T
A = 25ºC
AVDD = 24 V
R
LOAD = 250 Ÿ
R1
R2
RLOAD
C1
DACx760
BOOST
IOUT
GND
Copyright © 2016, Texas Instruments Incorporated
36
DAC7760, DAC8760
SBAS528B – JUNE 2013 – REVISED JUNE 2016
www.ti.com
Product Folder Links: DAC7760 DAC8760
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
8.4.2 Boost Configuration for IOUT
An external NPN transistor can be used as shown in Figure 87 to reduce power dissipation on the die. Most of
the load current flows through the NPN transistor with a small amount flowing through the on-chip PMOS
transistor based on the gain of the NPN transistor. This reduces the temperature induced drift on the die and
internal reference and is an option for use cases at the extreme end of the supply, load current, and ambient
temperature ranges. Resistor R2 stabilizes this circuit for cases where the RLOAD is a short or a very small load
like a multimeter. Recommended values for R1, R2 and C1 in this circuit are 1 kΩ, 20 Ω and 0.22 µF. An
equivalent solution is to place R2 (with a recommended value of 2 kΩ instead of the 20 Ω) in series with the base
of the transistor instead of the configuration shown in Figure 87. Note that there is some gain error introduced by
this configuration as seen in Figure 47 for the 0-mA to 24-mA range. TI recommends using the internal transistor
in most cases as the values in the Electrical Characteristics are based on the configuration with the internal on-
chip PMOS transitor.
Figure 87. Boost Mode Configuration
8.4.3 Filtering the Current Output (only on the VQFN package)
The VQFN package provides access to internal nodes of the circuit as shown in Figure 93. Capacitors can be
placed on these pins and AVDD to form a filter on the output current, reducing bandwidth and the slew rate of
the output. However, to achieve large reductions in slew rate, the programmable slew rate can be used to avoid
having to use large capacitors. Even in that case, the capacitors on CAP1 and CAP2 can be used to smooth out
the stairsteps caused by the digital code changes as shown in Figure 88. However, note that power supply ripple
also couples into the part through these capacitors.
Figure 88. IOUT vs Time for Different Capacitor Values on CAP1 and CAP2
8.4.4 HART Interface
On the DACx760, HART digital communication can be modulated onto the input signal by two methods:



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