DAC7760IPWPR datasheet(37/63 Pages) TI1

37 / 63 page

Bit

Boundary

Phase

Continuous

2200 Hz

(space)

1200 Hz

(mark)

Time

5.5 mA

6.5 mA

6.0 mA

Bit Cell Time = 833 s

DAC7760, DAC8760

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SBAS528B – JUNE 2013 – REVISED JUNE 2016

Product Folder Links: DAC7760 DAC8760

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8.4.4.1 For 4-mA to 20-mA Mode

This method is limited to the case where the RANGE bits of the Table 17 are programmed to the 4-mA to 20-mA

range. Some applications require going beyond the 4-mA to 20-mA range. In those cases, see second method

described in this section.

The external HART signal (ac voltage; 500 mVPP, 1200 Hz and 2200 Hz) can be capacitively coupled in through

the HART-IN pin and transferred to a current that is superimposed on the 4-mA to 20-mA current output. The

HART-IN pin has a typical input impedance of 35 kΩ that together with the input capacitor used to couple the

external HART signal forms a filter to attenuate frequencies beyond the HART band-pass region. In addition to

this filter, an external passive filter is recommended to complete the filtering requirements of the HART

specifications. Figure 89 illustrates the output current versus time operation for a typical HART signal.

Note:

DC current = 6 mA.

Figure 89. Output Current vs Time

Table 11 specifies the performance of the HART-IN pin.

Table 11. HART-IN Pin Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input impedance

HART signal ac-coupled into pin

kΩ

Output current (peak-to-peak)

Input signal of 500 mV (peak-to-peak)

0.9

1.1

8.4.4.2 For All Current Output Modes

The use of the HART-IN pin to implement HART modulation is limited to the case where the RANGE bits of the

Table 17 are set to the 4-mA to 20-mA range. To implement HART in all current-output modes, see

Implementing HART in All Current Output Modes.

8.5 Programming

8.5.1 Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates at

clock rates of up to 30 MHz and is compatible with SPI, QSPI™, Microwire, and digital signal processing (DSP)

standards. The SPI communication command consists of a write address byte and a data word for a total of 24

bits. The timing for the digital interface is shown in Figure 1, Figure 2, and Figure 3.

8.5.1.1 SPI Shift Register

The default frame is 24 bits wide (refer to the Frame Error Checking section for 32-bit frame mode) and begins

with the rising edge of SCLK that clocks in the MSB. The subsequent bits are latched on successive rising edges

of SCLK. The default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as

shown in Table 12.

DAC7760IPWPR Datasheet(PDF) 37 Page - Texas Instruments

DAC7760IPWPR Datasheet(HTML) 37 Page - Texas Instruments

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