DP83916 datasheet(33/96 Pages) NSC

33 / 96 page

40 SONIC-16 Registers (Continued)

434 Transmit Control Register

(RAk50l e 3h)

This register is used to program the SONIC-16’s transmit actions and provide status information after a packet has been

transmitted

(Figure 4-7) At the beginning of transmission bits 15 14 13 and 12 from the TXpktconfig field are loaded into the

TCR to configure the various transmit modes (see section 3511) When the transmission ends bits 10 – 0 indicate status

information and are set to a ‘‘1’’ when the corresponding condition is true These bits along with the number of collisions

information are written into the TXpktstatus field at the end of transmission (see section 3512) Bits 9 and 5 are cleared after

the TXpktstatus field has been written Bits 10 7 6 and 1 are cleared at the commencement of the next transmission while bit 8

is set at this time

A hardware reset sets bits 8 and 1 to a ‘‘1’’ This register is unaffected by a software reset

PINTR POWC CRCI EXDIS

EXD

DEF NCRS CRSL

EXC

OWC

PMB

BCM

PTX

reread only rwereadwrite

FIGURE 4-7 Transmit Control Register

Field

Meaning

PINTR PROGRAMMABLE INTERRUPT

POWC PROGRAMMED OUT OF WINDOW COLLISION TIMER

CRCI

CRC INHIBIT

EXDIS DISABLE EXCESSIVE DEFERAL TIMER

EXD

EXCESSIVE DEFERRAL

DEF

DEFERRED TRANSMISSION

NCRS

NO CRS

CRSL

CRS LOST

EXC

EXCESSIVE COLLISIONS

OWC

OUT OF WINDOW COLLISION

PMB

PACKET MONITORED BAD

FIFO UNDERRUN

BCM

BYTE COUNT MISMATCH

PTX

PACKET TRANSMITTED OK

Bit

Description

PINTR PROGRAMMABLE INTERRUPT

This bit allows transmit interrupts to be generated under software control The SONIC-16 will issue an interrupt (PINT

in the Interrupt Status Register) immediately after reading a TDA and detecting that PINTR is set in the TXpktconfig

field

Note

In order for PINTR to operate properly it must be set and reset in the TXpktconfig field by alternating TDAs This is necessary because after

PINT has been issued in the ISR PINTR in the Transmit Control Register must be cleared before it is set again in order to have the interrupt issued

for another packet The only effective way to do this is to set PINTR toa1no more often than every other packet

POWC PROGRAM ‘‘OUT OF WINDOW COLLISION’’ TIMER

This bit programs when the out of window collision timer begins

0 timer begins after the Start of Frame Delimiter (SFD)

1 timer begins after the first bit of preamble

CRCI CRC INHIBIT

0 transmit packet with 4-byte FCS field

1 transmit packet without 4-byte FCS field

EXDIS DISABLE EXCESSIVE DEFERRAL TIMER

0 excessive deferral timer enabled

1 excessive deferral timer disabled

Must be 0

EXD EXCESSIVE DEFERRAL

Indicates that the SONIC-16 has been deferring for 32 ms The transmission is aborted if the excessive deferral

timer is enabled (ie EXDIS is reset) This bit can only be set if the excessive deferral timer is enabled

DP83916 Datasheet(PDF) 33 Page - National Semiconductor (TI)

DP83916 Datasheet(HTML) 33 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL