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DP83916 Datasheet(PDF) 75 Page - National Semiconductor (TI) |
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DP83916 Datasheet(HTML) 75 Page - National Semiconductor (TI) |
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75 / 96 page  70 AC and DC Specifications (Continued) MEMORY READ BMODE e 0 SYNCHRONOUS MODE (one wait-state shown) TLF11722 – 62 Number Parameter 20 MHz Units Min Max T9 BSCK to Address Valid 34 ns T10 Address Hold Time from BSCK 5 ns T11 BSCK to ADS ECS Low 34 ns T12 BSCK to ADS ECS High 34 ns T15 ADS High Width (Note 2) bcyc b 5ns T23 Read Data Setup Time to BSCK 12 ns T24 Read Data Hold Time from BSCK 7 ns T28 BSCK to MWR (Read) Valid (Note 1) 30 ns T32 RDYi Setup Time to BSCK 30 ns T33 RDYi Hold Time to BSCK 5 ns Note 1 For successive read operations MWR remains low and for successive write operations MWR remains high During RBA and TBA transfers the MWR signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state that is inserted between the read and the write operation Note 2 bcyc e bus clock cycle time (T3) 75 |
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