DP83916 datasheet(79/96 Pages) NSC

79 / 96 page

70 AC and DC Specifications (Continued)

MEMORY READ BMODE e 1 SYNCHRONOUS MODE (one wait-state shown)

TLF11722 – 66

Number

Parameter

20 MHz

Units

Min

Max

BSCK to Address Valid

T10

Address Hold Time from BSCK

T11a

BSCK to AS DS ECS Low

T12a

BSCK to AS ECS High

T13a

BSCK to DS High

T14

AS Strobe Low Width (Note 3)

bcyc b 7ns

T15a

AS Strobe High Width (Note 3)

bcyc b 15

T16

Read Data Strobe High Width (Note 3)

bcyc b 12

T17

Read Data Strobe Low Width (Note 3)

bcyc b 5ns

T22

Address Valid to AS (Note 3)

bch b 18

T23a

Read Data Setup Time to BSCK

T24a

Read Data Hold Time from BSCK

T28

BSCK to MRW (Read) Valid (Note 1)

T30

DSACK01 Setup to BSCK (Note 2)

T31

DSACK01 Hold from BSCK

Note 1

For successive read operations MWR remains low and for successive write operations MWR remains high During RBA and TBA transfers the MWR

signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state

that is inserted between the read and the write operation

Note 2

DSACK01 must be synchronized to the bus clock (BSCK) during synchronous mode

Note 3

bcyc e bus clock cycle time (T3) bch e bus clock high time (T2)

DP83916 Datasheet(PDF) 79 Page - National Semiconductor (TI)

DP83916 Datasheet(HTML) 79 Page - National Semiconductor (TI)

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