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DP83916 Datasheet(PDF) 74 Page - National Semiconductor (TI) |
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DP83916 Datasheet(HTML) 74 Page - National Semiconductor (TI) |
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74 / 96 page  70 AC and DC Specifications (Continued) MEMORY WRITE BMODE e 0 SYNCHRONOUS MODE (one wait-state shown) TLF11722 – 61 Number Parameter 20 MHz Units Min Max T9 BSCK to Address Valid 34 ns T10 Address Hold Time from BSCK 5 ns T11 BSCK to ADS ECS Low 34 ns T12 BSCK to ADS ECS High 34 ns T15 ADS High Width (Note 2) bcyc-5 ns T32 RDYi Setup to BSCK 30 ns T33 RDYi Hold from BSCK 5 ns T36 BSCK to Memory Write Data Valid 70 ns T37 BSCK to MWR (Write) Valid (Note 1) 30 ns T40 Write Data Hold Time from BSCK 10 ns Note 1 For successive read operations MWR remains low and for successive write operations MWR remains high during a transfer During RDA and TDA transfers the MWR signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state that is inserted between the read and the write operation Note 2 bcyc e bus clock cycle time (T3) 74 |
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