DP83916 datasheet(83/96 Pages) NSC

83 / 96 page

70 AC and DC Specifications (Continued)

BUS REQUEST TIMING BMODE e 1

TLF11722 – 70

Number

Parameter

20 MHz

Units

Min

Max

T45a

BG Asynchronous Setup Time to BSCK

T47

BSCK Low to BR Low

T48

BSCK Low to BR TRI-STATE (Note 4)

T49

BSCK High to BGACK Low (Note 1)

T50

BSCK High to BGACK High (Note 5)

T51a

BSCK to Address AS MRW DS ECS

USRk10l and EXUSRk30l TRI-STATE (Note 4)

T52

BSCK to Data TRI-STATE (Note 4)

T53

BSCK to USRk10l Valid

T55

BSCK to Bus Status

Idle to Non-Idle

T55a

BSCK to Bus Status

Non-Idle to Idle (Note 3)

T55b

Sk20l Hold from BSCK

Note 1

BGACK is only issued if BG is low and AS DSACK01 STERM and BGACK are deasserted

Note 2

For specific timing on these signals driven by the SONIC-16 see the memory read and memory write timing diagrams on previous pages

Note 3

Sk20l will inidicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation

Note 4

This timing value includes an RC delay inherent in our test measurement These signals typically TRI-STATE 7 ns eariler enabling other devices to drive

these lines without contention

Note 5

BGACK is driven high for approximately

BSCK before going TRI-STATE

DP83916 Datasheet(PDF) 83 Page - National Semiconductor (TI)

DP83916 Datasheet(HTML) 83 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL