DP83916 datasheet(34/96 Pages) NSC

34 / 96 page

40 SONIC-16 Registers (Continued)

434 Transmit Control Register

(Continued)

(RAk50l e 3h)

Bit

Description

DEF DEFERRED TRANSMISSION

Indicates that the SONIC-16 has deferred its transmission during the first attempt If subsequent collisions occur this

bit is reset This bit is cleared after the TXpktstatus field is written in the TDA

NCRS NO CRS

Indicates that Carrier Sense (CRS) was not present during transmission CRS is monitored from the beginning of the

Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted This bit is set at the start

of preamble and is reset if CRS is detected Hence if CRS is never detected throughout the entire transmission of

the packet this bit will remain set

Note

NCRS will always remain set in MAC loopback

CRSL CRS LOST

Indicates that CRS has gone low or has not been present during transmission CRS is monitored from the beginning

of the Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted

Note

if CRS was never present both NCRS and CRSL will be set simultaneously Also CRSL will always be set in MAC loopback

EXC EXCESSIVE COLLISIONS

Indicates that 16 collisions have occurred The transmission is aborted

OWC OUT OF WINDOW COLLISION

Indicates that an illegal collision has occurred after 512 ms (one slot time) from either the first bit of preamble or

from SFD depending upon the POWC bit The transmission backs off as in a normal transmission This bit is cleared

after the TXpktstatus field is written in the TDA

Must be 0

PMB PACKET MONITORED BAD

This bit is set if after the receive unit has monitored the transmitted packet the CRC has been calculated as invalid

a frame alignment error occurred or the Source Address does not match any of the CAM address registers

Note 1

The SONIC-16’s CRC checker is active during transmission

Note 2

If CRC has been inhibited for transmissions (CRCI is set) this bit will always be low This is true regardless of Frame Alignment or Source

Address mismatch errors

Note 3

If a Receive FIFO overrun has occurred the transmitted packet is not monitored completely Thus if PMB is set along with the RFO bit in the

ISR then PMB has no meaning The packet must be completely received before PMB has meaning

FU FIFO UNDERRUN

Indicates that the SONIC-16 has not been able to access the bus before the FIFO has emptied This condition

occurs from excessive bus latency andor slow bus clock The transmission is aborted (See section 142)

BCM BYTE COUNT MISMATCH

This bit is set when the SONIC-16 detects that the TXpktpkt

size field is not equal to the sum of the

TXpktfrag

size field(s) Transmission is aborted

PTX PACKET TRANSMITTED OK

Indicates that a packet has been transmitted without the following errors

Excessive Collisions (EXC)

Excessive Deferral (EXD)

FIFO Underrun (FU)

Byte Count Mismatch (BCM)

DP83916 Datasheet(PDF) 34 Page - National Semiconductor (TI)

DP83916 Datasheet(HTML) 34 Page - National Semiconductor (TI)

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