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WM5102 Datasheet(PDF) 35 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 35 Page - Wolfson Microelectronics plc

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Production Data
WM5102
w
PD, June 2014, Rev 4.2
35
DIGITAL AUDIO INTERFACE - SLAVE MODE
Figure 7 Audio Interface Timing - Slave Mode
Note that BCLK and LRCLK inputs can be inverted if required; Figure 7 shows the default, non-
inverted polarity.
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing - Slave Mode
AIFnBCLK cycle time
tBCY
80
ns
AIFnBCLK pulse width high
tBCH
12
ns
AIFnBCLK pulse width low
tBCL
12
ns
AIFn[TX/RX]LRCLK set-up time to BCLK rising edge
tLRSU
7
ns
AIFn[TX/RX]LRCLK hold time from BCLK rising edge
tLRH
5
ns
AIFnRXDAT hold time from BCLK rising edge
tDH
5
ns
AIFnTXDAT propagation delay from BCLK falling edge
tDD
0
12
ns
AIFnRXDAT set-up time to BCLK rising edge
tDSU
7
ns
Notes:
The descriptions above assume non-inverted polarity of AIFnBCLK.
When AIFnBCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be
within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.



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