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WM5102 Datasheet(PDF) 33 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 33 Page - Wolfson Microelectronics plc |
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33 / 334 page ![]() Production Data WM5102 w PD, June 2014, Rev 4.2 33 DIGITAL SPEAKER (PDM) INTERFACE TIMING Figure 4 Digital Speaker (PDM) Interface Timing - Mode A Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT PDM Audio Interface Timing SPKCLK cycle time tCY 160 163 358 ns SPKCLK duty cycle 45 55 % SPKCLK rise/fall time (DBVDD=1.8V, 25pF load) tr, tf 5 30 ns SPKDAT set-up time to SPKCLKn rising edge (Left channel) tLSU 30 ns SPKDAT hold time from SPKCLKn rising edge (Left channel) tLH 30 ns SPKDAT set-up time to SPKCLKn falling edge (Right channel) tRSU 30 ns SPKDAT hold time from SPKCLKn falling edge (Right channel) tRH 30 ns Figure 5 Digital Speaker (PDM) Interface Timing - Mode B Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT PDM Audio Interface Timing SPKCLK cycle time tCY 160 163 358 ns SPKCLK duty cycle 45 55 % SPKCLK rise/fall time (DBVDD=1.8V, 25pF load) tr, tf 5 30 ns SPKDAT enable from SPKCLK rising edge (Right channel) tREN 15 ns SPKDAT disable to SPKCLK falling edge (Right channel) tRDIS 5 ns SPKDAT enable from SPKCLK falling edge (Left channel) tLEN 15 ns SPKDAT disable to SPKCLK rising edge (Left channel) tLDIS 5 ns |
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