WM5102 datasheet(46/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

ANALOGUE LINE INPUT

Line inputs can be connected to the WM5102 in a similar manner to the microphone inputs described

above. Single-ended and differential modes are supported on each of the six input paths.

The applicable mode (single-ended or differential) is selected using the INn_MODE registers, as

described later. Note that the mode is configurable for each stereo pair of inputs; the Left and Right

channels of any pair of inputs are always in the same mode.

The analogue line input configurations are illustrated in Figure 18 and Figure 19. Note that the

microphone bias (MICBIAS) is not used for line input connections.

Figure 18 Single-Ended Line Input

Figure 19 Differential Line Input

DIGITAL MICROPHONE INPUT

Up to six digital microphones can be connected to the WM5102. The digital microphone mode is

selected using the INn_MODE registers, as described later. Note that the mode is configurable for

each stereo pair of inputs; the Left and Right channels of any pair of inputs are always in the same

mode.

In digital microphone mode, two channels of audio data are multiplexed on the DMICDAT1,

DMICDAT2 or DMICDAT3 pins. Each of these stereo interfaces is clocked using the respective

DMICCLK1, DMICCLK2 or DMICCLK3 pin.

When digital microphone input is enabled, the WM5102 outputs a clock signal on the applicable

DMICCLKn pin(s). The DMICCLKn frequency is controlled by the respective INn_OSR register, as

described in Table 1. See Table 3 for details of the INn_OSR registers.

Note that the DMICCLKn frequencies noted in Table 1 assume that the SYSCLK frequency is a

multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz

(SYSCLK_FRAC=1), then the DMICCLKn frequencies will be scaled accordingly.

CONDITION

DMICCLKn FREQUENCY

INn_OSR = 00

1.536MHz

INn_OSR = 01

3.072MHz

Table 1 DMICCLK Frequency

The voltage reference for each digital microphone interface is selectable, using the INn_DMIC_SUP

registers. Each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3

levels.

A pair of digital microphones is connected as illustrated in Figure 20. The microphones must be

configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic

transmits a data bit when DMICCLK is low. The WM5102 samples the digital microphone data at the

end of each DMICCLK phase. Each microphone must tri-state its data output when the other

microphone is transmitting.

Note that the WM5102 provides integrated pull-down resistors on the DMICDAT1, DMICDAT2 and

DMICDAT3 pins. This provides a flexible capability for interfacing with other devices.

WM5102 Datasheet(PDF) 46 Page - Wolfson Microelectronics plc

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