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WM5102 Datasheet(PDF) 78 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 78 Page - Wolfson Microelectronics plc

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WM5102
Production Data
w
PD, June 2014, Rev 4.2
78
GPIO Outputs from DRC
The Dynamic Range Control (DRC) circuit provides a number of status outputs, which can be output
directly on a GPIO pin as an external indication of the DRC Status. See “General Purpose Input /
Output” to configure a GPIO pin for these functions.
Each of the DRC status outputs is described below.
The DRC Signal Detect flag indicates that a signal is present on the respective signal path. The
threshold level for signal detection is configurable using the register fields are described in Table 14.
The DRC Anti-Clip flag indicates that the DRC Anti-Clip function has been triggered. In this event, the
DRC gain is decreasing in response to a rising signal level. The flag is asserted until the DRC gain
stablises.
The DRC Decay flag indicates that the DRC gain is increasing in response to a low level signal input.
The flag is asserted until the DRC gain stabilises.
The DRC Noise Gate flag indicates that the DRC Noise Gate function has been triggered, indicating
that an idle condition has been detected in the signal path.
The DRC Quick Release flag indicates that the DRC Quick Release function has been triggered. In
this event, the DRC gain is increasing rapidly following detection of a short transient peak. The flag is
asserted until the DRC gain stabilises.
DRC Register Controls
The DRC control registers are described in Table 14.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3585
(0E01h)
FX_Ctrl2
15:4
FX_STS [11:0]
000h
LHPF, DRC, EQ Enable Status
Indicates the status of each of the
respective signal processing
functions.
[11] = EQ4
[10] = EQ3
[9] = EQ2
[8] = EQ1
[7] = Reserved
[6] = Reserved
[5] = DRC1 (Right)
[4] = DRC1 (Left)
[3] = LHPF4
[2] = LHPF3
[1] = LHPF2
[0] = LHPF1
Each bit is coded as:
0 = Disabled
1 = Enabled
R3712
(0E80h)
DRC1 ctrl1
15:11
DRC1_SIG_DET
_RMS [4:0]
00h
DRC1 Signal Detect RMS
Threshold.
This is the RMS signal level for
signal detect to be indicated when
DRC1_SIG_DET_MODE=1.
00h = -30dB
01h = -31.5dB
…. (1.5dB steps)
1Eh = -75dB
1Fh = -76.5dB



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