TMS320C54CST datasheet(21/171 Pages) TI

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Introduction

November 2001 − Revised September 2003

SPRS187B

2.3

Signal Descriptions

Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact

pin locations based on package type.

Table 2−3. Signal Descriptions

TERMINAL

NAME

I/O†

DESCRIPTION

EXTERNAL MEMORY INTERFACE PINS

A22(MSB)

A21

A20

A19

A18

A17

A16

O/Z

Parallel address bus A22 (MSB) through A0 (LSB). The lower sixteen address pins—A0 to A15—are

multiplexed to address all external memory (program, data) or I/O, while the upper seven address

pins—A22 to A16—are only used to address external program space. These pins are placed in the

high-impedance state when the hold mode is enabled, or when OFF is low.

A15

A14

A13

A12

A11

A10

A0(LSB)

A15(MSB)

A14

A13

A12

A11

A10

A0(LSB)

These pins can be used to address internal memory via the HPI when the HPI16

pin is high.

D15(MSB)

D14

D13

D12

D11

D10

D0(LSB)

I/O/Z

D15(MSB)

D14

D13

D12

D11

D10

D0(LSB)

I/O

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins, D0 to

D15, are multiplexed to transfer data between the core CPU and external

data/program memory, I/O devices, or HPI in 16-bit mode. The data bus is

placed in the high-impedance state when not outputting or when RS or HOLD is

asserted. The data bus also goes into the high-impedance state when OFF is

low.

The data bus includes bus holders to reduce the static power dissipation caused

by floating, unused pins. The bus holders also eliminate the need for external

bias resistors on unused pins. When the data bus is not being driven by the

DSP, the bus holders keep the pins at the logic level that was most recently

driven. The data bus holders of the DSP are disabled at reset, and can be

enabled/disabled via the BH bit of the BSCR.

INITIALIZATION, INTERRUPT, AND RESET PINS

IACK

O/Z

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching

the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when OFF

is low.

INT0

INT1

INT2

INT3

External user interrupt inputs. INT0-3 are prioritized and maskable via the interrupt mask register and

interrupt mode bit. The status of these pins can be polled by way of the interrupt flag register.

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.

When NMI is activated, the processor traps to the appropriate vector location.

† I = Input, O = Output, Z = High-impedance, S = Supply

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