TMS320C54CST datasheet(22/171 Pages) TI

22 / 171 page

Introduction

November 2001 − Revised September 2003

SPRS187B

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

DESCRIPTION

I/O†

INITIALIZATION, INTERRUPT, AND RESET PINS (CONTINUED)

Reset input. RS causes the DSP to terminate execution and causes a re-initialization of the CPU and

peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory.

RS affects various registers and status bits.

MP/MC

Microprocessor/microcomputer mode select pin. If active low at reset, microcomputer mode is selected, and

the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is

driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program

space. This pin is only sampled at reset, and the MP/MC bit of the PMST register can override the mode

that is selected at reset.

MULTIPROCESSING AND GENERAL PURPOSE PINS

BIO

Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor

executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline

for XC instruction, and all other instructions sample BIO during the read phase of the pipeline.

O/Z

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set

low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor

configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,

and is set high at reset.

MEMORY CONTROL PINS

O/Z

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for

accessing a particular external memory space. Active period corresponds to valid address information.

Placed into a high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state

when OFF is low.

MSTRB

O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access

to data or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the

high-impedance state when OFF is low.

READY

Data ready input. READY indicates that an external device is prepared for a bus transaction to be

completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY

again. Note that the processor performs ready detection if at least two software wait states are

programmed. The READY signal is not sampled until the completion of the software wait states.

R/W

O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device. Normally in

read mode (high), unless asserted low when the DSP performs a write operation. Placed in high-impedance

state in hold mode. R/W also goes into the high-impedance state when OFF is low.

IOSTRB

O/Z

I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an

I/O device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state

when OFF is low.

HOLD

Hold input. HOLD is asserted to request control of the address, data, and control lines. When

acknowledged by the C54x

 DSP, these lines go into high-impedance state.

HOLDA

O/Z

Hold acknowledge signal. HOLDA indicates that the DSP is in a hold state and that the address, data, and

control lines are in a high-impedance state, allowing the external memory interface to be accessed by other

devices. HOLDA also goes into the high-impedance state when is OFF low.

MSC

O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait

states are enabled, the MSC pin goes active at the beginning of the first software wait state, and goes

inactive (high) at the beginning of the last software wait state. If connected to the ready input, MSC forces

one external wait state after the last internal wait state is completed. MSC also goes into the high

impedance state when OFF is low.

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the

address bus and goes into the high-impedance state when OFF is low.

† I = Input, O = Output, Z = High-impedance, S = Supply

C54x is a trademark of Texas Instruments.

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