TMS320VC5407 datasheet(104/110 Pages) TI

104 / 110 page

Electrical Specifications

104

November 2001 − Revised April 2004

SPRS007D

5.15.2

HPI16 Mode

Table 5−35 and Table 5−36 assume testing over recommended operating conditions and P = 0.5 * processor

clock (see Figure 5−32 through Figure 5−34). In the following tables, DS refers to the logical OR of HCS,

HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are

shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,

Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.

Table 5−35. HPI16 Mode Timing Requirements

MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HR/W valid before DS falling edge

th(DSL-HBV)

Hold time, HR/W valid after DS falling edge

tsu(HAV-DSH)

Setup time, address valid before DS rising edge (write)

tsu(HAV-DSL)

Setup time, address valid before DS falling edge (read)

−(4P − 6)

th(DSH-HAV)

Hold time, address valid after DS rising edge

tw(DSL)

Pulse duration, DS low

tw(DSH)

Pulse duration, DS high

Memory accesses with no DMA activity

Reads

10P + 30

Memory accesses with no DMA activity.

Writes

10P + 10

Cycle time, DS rising edge to

Memory accesses with 16 bit DMA activity

Reads

16P + 30

tc(DSH-DSH)

Cycle time, DS rising edge to

next DS rising edge

Memory accesses with 16-bit DMA activity.

Writes

16P + 10

Memory accesses with 32 bit DMA activity

Reads

24P + 30

Memory accesses with 32-bit DMA activity.

Writes

24P + 10

tsu(HDV-DSH)W

Setup time, HD valid before DS rising edge

th(DSH-HDV)W

Hold time, HD valid after DS rising edge, write

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