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TMS320VC5407 Datasheet(PDF) 105 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 105 Page - Texas Instruments |
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105 / 110 page  Electrical Specifications 105 November 2001 − Revised April 2004 SPRS007D Table 5−36. HPI16 Mode Switching Characteristics PARAMETER MIN MAX UNIT td(DSL-HDD) Delay time, DS low to HD driven 0 10 ns Case 1a: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and tw(DSH) was < 18H 32P + 20 − tw(DSH) Case 1b: Memory accesses not immediately following a write when DMAC is active in 16-bit mode 16P + 20 t Delay time, DS low to HD valid for first Case 1c: Memory accesses initiated immediately following a write when DMAC is active in 32-bit mode and tw(DSH) was < 26H 48P + 20 − tw(DSH) ns td(DSL-HDV1) valid for first word of an HPI read Case 1d: Memory access not immediately following a write when DMAC is active in 32-bit mode 24P + 20 ns HPI read Case 2a: Memory accesses initiated immediately following a write when DMAC is inactive and tw(DSH) was < 10H 20P + 20 − tw(DSH) Case 2b: Memory accesses not immediately following a write when DMAC is inactive 10P + 20 Delay time Memory writes when no DMA is active 10P + 5 td(DSH-HYH) Delay time, DS high to Memory writes with one or more 16-bit DMA channels active 16P + 5 ns d(DSH HYH) DS high to HRDY high Memory writes with one or more 32-bit DMA channels active 24P + 5 tv(HYH-HDV) Valid time, HD valid after HRDY high 7 ns th(DSH-HDV)R Hold time, HD valid after DS rising edge, read 1 6 ns td(COH-HYH) Delay time, CLKOUT rising edge to HRDY high 5 ns td(DSL-HYL) Delay time, DS low to HRDY low 12 ns td(DSH−HYL) Delay time, DS high to HRDY low 12 ns tc(DSH−DSH) tw(DSH) tsu(HBV−DSL) tw(DSL) th(DSL−HBV) tsu(HAV−DSL) th(DSH−HDV)R tv(HYH−HDV) td(DSL−HYL) HCS HDS HR/W HA[17:0] HD[15:0] HRDY Valid Address Data Valid Address th(DSL−HBV) td(DSL−HDV1) Data td(DSL−HDV1) tv(HYH−HDV) th(DSH−HDV)R td(DSL−HYL) th(DSH−HAV) td(DSL−HDD) td(DSL−HDD) tsu(HBV−DSL) Figure 5−32. Nonmultiplexed Read Timings |
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