LAN9115 datasheet(61/114 Pages) MICROCHIP

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DS00002269A-page 61

LAN9115

5.3.1

ID_REV—CHIP ID AND REVISION

This register contains the ID and Revision fields for this design.

5.3.2

IRQ_CFG—INTERRUPT CONFIGURATION REGISTER

This register configures and indicates the state of the IRQ signal.

Offset:

50h

Size:

32 bits

Bits

Description

Type

Default

31-16

Chip ID. This read-only field identifies this design

0115h

15-0

Chip Revision. This is the current revision of the chip.

0001h

Offset:

54h

Size:

32 bits

Bits

Description

Type

Default

31:24

Interrupt Deassertion Interval (INT_DEAS). This field determines the

Interrupt Deassertion Interval for the Interrupt Request in multiples of 10

microseconds.

Writing zeros to this field disables the INT_DEAS Interval and resets the

interval counter. Any pending interrupts are then issued. If a new, non-

zero value is written to the INT_DEAS field, any subsequent interrupts will

obey the new setting.

Note:

The Interrupt Deassertion interval does not apply to the PME

interrupt.

R/W

23-15

Reserved

Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one to

this register clears the de-assertion counter in the IRQ Controller, thus

causing a new de-assertion interval to begin (regardless of whether or not

the IRQ Controller is currently in an active de-assertion interval).

Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit

indicates that the INT_DEAS is currently in a deassertion interval, and any

interrupts (as indicated by the IRQ_INT and INT_EN bits) will not be

delivered to the IRQ pin. When cleared, the INT_DEAS is currently not in

a deassertion interval, and enabled interrupts will be delivered to the IRQ

pin.

Master Interrupt (IRQ_INT). This read-only bit indicates the state of the

internal IRQ line. When set high, one of the enabled interrupts is currently

active. This bit will respond to the associated interrupts regardless of the

IRQ_EN field. This bit is not affected by the setting of the INT_DEAS field.

11-9

Reserved

IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the

IRQ pin. When cleared, the IRQ output is disabled and will be

permanently deasserted. This bit only controls the external IRQ signal,

and has no effect on any of the internal interrupt status bits.

R/W

7-5

Reserved

IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function

as an active low output. When set, the IRQ output is active high. When

IRQ is configured as an open-drain output this field is ignored, and the

interrupt output is always active low.

R/W NASR

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