LAN9115 datasheet(12/114 Pages) MICROCHIP

12 / 114 page

LAN9115

DS00002269A-page 12

 2005-2016 Microchip Technology Inc.

100, 99,

General Purpose I/O

data,

nLED1 (Speed

Indicator),

nLED2 (Link &

Activity Indicator),

nLED3 (Full-

Duplex Indicator).

GPIO[2:0]/

LED[3:1]

IS/O12/

OD12

General Purpose I/O data: These

three general-purpose signals are fully

programmable as either push-pull

output, open-drain output or input by

writing the GPIO_CFG configuration

multiplexed as GP LED connections.

GPIO signals are Schmitt-triggered

inputs. When configured as LED

outputs these signals are open-drain.

nLED1 (Speed Indicator). This signal

is driven low when the operating speed

is 100Mbs, during auto-negotiation and

when the cable is disconnected. This

signal is driven high only during 10Mbs

operation.

nLED2 (Link & Activity Indicator).

This signal is driven low (LED on)

when the LAN9115 detects a valid link.

This signal is pulsed high (LED off) for

80mS whenever transmit or receive

activity is detected. This signal is then

driven low again for a minimum of

80mS, after which time it will repeat the

process if TX or RX activity is detected.

Effectively, LED2 is activated solid for a

link. When transmit or receive activity

is sensed LED2 will flash as an activity

indicator.

nLED3 (Full-Duplex Indicator). This

signal is driven low when the link is

operating in full-duplex mode.

RBIAS

PLL Bias: Connect to an external

12.0K ohm 1.0% resistor to ground.

Used for the PLL Bias circuit.

Test Pin

ATEST

This pin must be connected to VDD for

normal operation.

Internal Regulator

Power

VREG

3.3V input for internal voltage regulator

20,28,3

42,48,5

5,61,97

+3.3V I/O Power

VDD_IO

+3.3V I/O logic power supply pins

19,27,3

4,41,47,

54,60,9

I/O Ground

GND_IO

Ground for I/O pins

81,85,8

+3.3V Analog Power

VDD_A

+3.3V Analog power supply pins. See

Note 2-1

77,80,8

6,88

Analog Ground

VSS_A

Ground for analog circuitry

3,65

Core Voltage

Decoupling

VDD_CORE

1.8 V from internal core regulator. Both

pins must be connected together

externally and then tied to a 10uF 0.1-

Ohm ESR capacitor, in parallel with a

0.01uF capacitor to Ground next to

each pin. These pins must not be used

to supply power to other external

devices. See Note 2-1

TABLE 2-5:

SYSTEM AND POWER SIGNALS (CONTINUED)

Pin No.

Name

Symbol

Buffer

Type

# Pins

Description

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