| Electronic Components Datasheet Search |
|
LAN9115 Datasheet(PDF) 75 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
LAN9115 Datasheet(HTML) 75 Page - Microchip Technology |
|
75 / 114 page ![]() 2005-2016 Microchip Technology Inc. DS00002269A-page 75 LAN9115 5.3.19 RX_DROP– RECEIVER DROPPED FRAMES COUNTER This register indicates the number of receive frames that have been dropped. 5.3.20 MAC_CSR_CMD – MAC CSR SYNCHRONIZER COMMAND REGISTER This register is used to control the read and write operations with the MAC CSR’s 5.3.21 MAC_CSR_DATA – MAC CSR SYNCHRONIZER DATA REGISTER This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s 5.3.22 AFC_CFG – AUTOMATIC FLOW CONTROL CONFIGURATION REGISTER This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Offset: A0h Size: 32 bits Bits Description Type Default 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). RC 00000000h Offset: A4h Size: 32 bits Bits Description Type Default 31 CSR Busy. When a 1 is written into this bit, the read or write operation is performed to the specified MAC CSR. This bit will remain set until the operation is complete. In the case of a read this means that the host can read valid data from the data register. The MAC_CSR_CMD and MAC_CSR_DATA registers should not be modified until this bit is cleared. SC 0 30 R/nW. When set, this bit indicates that the host is requesting a read operation. When clear, the host is performing a write. R/W 0 29-8 Reserved. RO - 7-0 CSR Address. The 8-bit value in this field selects which MAC CSR will be accessed with the read or write operation. R/W 00h Offset: A8h Size: 32 bits Bits Description Type Default 31-0 MAC CSR Data. Value read from or written to the MAC CSR’s. R/W 00000000h Offset: ACh Size: 32 bits Note: The LAN9115 will not transmit pause frames or assert back pressure if the transmitter is disabled. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |