Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

WM8776 Datasheet(PDF) 24 Page - Wolfson Microelectronics plc

Part # WM8776
Description  24 BIT 192KHZ STEREO CODEC WITH 5 CHANNEL I/P MULTIPLEXER
PDF  55 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8776 Datasheet(HTML) 24 Page - Wolfson Microelectronics plc

Back Button WM8776 Datasheet HTML 20Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 21Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 22Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 23Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 24Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 25Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 26Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 27Page - Wolfson Microelectronics plc WM8776 Datasheet HTML 28Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 55 page
background image
WM8776
Product Preview
w
PP Rev 1.91 June 2004
24
Note: In 24 bit I
2S mode, any width of 24 bits or less is supported provided that
ADCLRC/DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is
applied to the DAC.
MASTER MODES
Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In
ADC Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8776.
In Slave mode ADCLRC and ADCBCLK are inputs to WM8776.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12 (0Ch)
0001100
Interface Control
9
ADCMS
0
Audio Interface Master/Slave Mode
select for ADC:
0 : Slave Mode
1: Master Mode
Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In
DAC Master mode DACLRC and DACBCLK are outputs and are generated by the WM8776.
In Slave mode DACLRC and DACBCLK are inputs to WM8776.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R12 (0Ch)
0001100
Interface Control
8
DACMS
0
Audio Interface Master/Slave Mode
select for DAC:
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT
In ADC Master mode the WM8776 generates ADCLRC and ADCBCLK, in DAC master mode
the WM8776 generates DACLRC and DACBCLK. These clocks are derived from the master
clock (ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to
DACLRC are set by ADCRATE and DACRATE respectively.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC
ratio select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
R12 (0Ch)
0001100
ADCLRC and DACLRC
frequency select
6:4
DACRATE[2:0]
010
Master Mode MCLK:DACLRC
ratio select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com