TNETV1644ZDU6 datasheet(37/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

GPIO.

For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND

HSYNC/EM_CS5/

IPD

flash.

F19

J22

I/O/Z

GP[33]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

CI7(CCD15) /

EM_A[13]/

IPD

B10

A12

I/O/Z

AD25/

DVDD33

EM_D[0]/GP[51]

CI6(CCD14) /

EM_A[14]/

IPD

A10

A13

I/O/Z

AD27/

DVDD33

EM_D[1]/GP[50]

CI5(CCD13) /

EM_A[15]/

IPD

B11

C13

I/O/Z

AD29/

DVDD33

EM_D[2]/GP[49]

CI4(CCD12) /

EM_A[16]/

IPD

C11

B13

I/O/Z

These pins are multiplexed between VPFE (CCDC), EMIFA (NAND),

PGNT/

DVDD33

PCI, and GPIO.

EM_D[3]/GP[48]

CI3(CCD11)/

For EMIFA (NAND) AEM[2:0] = 011, these pins are the 8-bit

EM_A[17]/

IPD

bi-directional data bus (EM_D[7:0]).

A11

B14

I/O/Z

AD31/

DVDD33

EM_D[4]/GP[47]

CI2(CCD10)/

EM_A[18]/

IPD

D11

A14

I/O/Z

PRST/

DVDD33

EM_D[5]/GP[46]

CI1(CCD9)/

EM_A[19]/

IPD

B12

C14

I/O/Z

PREQ/

DVDD33

EM_D[6]/GP[45]

CI0(CCD8)/

EM_A[20]/

IPD

C12

C15

I/O/Z

PINTA/

DVDD33

EM_D[7]/GP[44]

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