TNETV1644ZDU6 datasheet(97/306 Pages) TI1

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3.6.2.1 HPI Control Register (HPICTL)

3.6.2.2 Timer Control Register (TIMERCTL)

TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

The HPI Control (HPICTL) register determines the Host Burst Write Time-Out value. The user should

only modify this register once during device initialization. When modifying this register, the user

must ensure the HPI FIFOs are empty and there are no on-going HPI transactions.

RESERVED

R-0000 0000 0000 0000

RESERVED

TIMOUT

R- 0000 00

R/W-00

R/W-1000 0000

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-8. HPICTL Register— 0x01C4 0030

Table 3-16. HPICTL Register Description

Bit

Field Name

Description

31:10

RESERVED Reserved. Read-only, writes have no effect.

9:8

RESERVED Reserved. For proper device operation, the user should only write "0" to these bits (default).

Host Burst Write Timeout Value

When the HPI time-out counter reaches the value programmed here, the HPI write FIFO content is flushed. For

7:0

TIMOUT

more details on the time-out counter and its use in write bursting, see the TMS320DM643x DMP Host Port

Interface (HPI) User's Guide (literature number SPRU998).

The Timer Control Register (TIMERCTL) provides additional control for Timer0 and Timer2. The user

should only modify this register once during device initialization, when the corresponding Timer is

not in use.

• Timer 2 Control: The TIMERCTL.WDRST bit determines if the WatchDog timer event (Timer 2) can

cause a device max reset. For more details on the description of a maximum reset, see Section 6.5.3,

Maximum Reset.

• Timer 0 Control: The TINP0SEL bit selects the clock source connected to Timer0's TIN0 input.

RESERVED

R-0000 0000 0000 0000

TINP0

RESERVED

SEL

RST

R- 0000 0000 0000 00

R/W-0

R/W-1

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-9. TIMERCTL Register— 0x01C4 0084

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