SPC56ECxx datasheet(97/123 Pages) STMICROELECTRONICS

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SPC564Bxx-SPC56ECxx

Electrical Characteristics

122

3.18.2

MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. In addition, the system clock frequency must

exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency

in 1:1 mode.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from

either the rising or falling edge of TX_CLK, and the timing is the same in either case. This

options allows the use of non-compliant MII PHYs.

Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74

Reference Manual for details of this option and how to enable it.

Figure 22. MII transmit signal timing diagram

3.18.3

MII Async Inputs Signal Timing (CRS and COL)

Table 46. MII transmit signal timing(1)

Spec

Characteristic

Min

Max

Unit

TX_CLK to TXD[3:0],

TX_EN, TX_ER invalid

5—

TX_CLK to TXD[3:0],

TX_EN, TX_ER valid

—25

TX_CLK pulse width high

35%

65%

TX_CLK period

TX_CLK pulse width low

35%

65%

TX_CLK period

Output pads configured with SRE = 0b11.

TX_CLK (input)

TXD[3:0] (outputs)

TX_EN

TX_ER

Table 47. MII Async Inputs Signal Timing(1)

Spec

Characteristic

Min

Max

Unit

CRS, COL minimum pulse width

1.5

—

TX_CLK period

Output pads configured with SRE = 0b11.

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